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riscv-gcc-1
Commit f1e77d83 by Ulrich Weigand Committed by Ulrich Weigand
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s390.md ("*mulsi3_sign"): New insn. 

	* config/s390/s390.md ("*mulsi3_sign"): New insn.
	("mulsidi3" expander, "mulsi_6432" insn): Remove, replace by ...
	("mulsidi3"): ... this new insn.
	("umulsidi3"): New insn.
	("divmoddi3", "divmodtidi3", "divmodtisi3"): Simplify by using
	mixed-mode matching constraints.
	("udivmodsi4", "udivmoddisi3"): New insns.
	("udivsi3", "umodsi3"): Use only in ESA/390 mode.

From-SVN: r70897
parent 7ae963b4
Showing with 110 additions and 48 deletions
gcc/ChangeLog
2003-08-28 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/s390.md ("*mulsi3_sign"): New insn.
("mulsidi3" expander, "mulsi_6432" insn): Remove, replace by ...
("mulsidi3"): ... this new insn.
("umulsidi3"): New insn.
("divmoddi3", "divmodtidi3", "divmodtisi3"): Simplify by using
mixed-mode matching constraints.
("udivmodsi4", "udivmoddisi3"): New insns.
("udivsi3", "umodsi3"): Use only in ESA/390 mode.
2003-08-28 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> 2003-08-28 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* builtin-types.def (BT_INT_PTR, BT_FLOAT_PTR, BT_DOUBLE_PTR, * builtin-types.def (BT_INT_PTR, BT_FLOAT_PTR, BT_DOUBLE_PTR,
......
gcc/config/s390/s390.md
...@@ -4023,7 +4023,6 @@ ...@@ -4023,7 +4023,6 @@
[(set_attr "op_type" "RRE,RXY") [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "imul")]) (set_attr "type" "imul")])
(define_insn "muldi3" (define_insn "muldi3"
[(set (match_operand:DI 0 "register_operand" "=d,d,d") [(set (match_operand:DI 0 "register_operand" "=d,d,d")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
...@@ -4040,6 +4039,15 @@ ...@@ -4040,6 +4039,15 @@
; mulsi3 instruction pattern(s). ; mulsi3 instruction pattern(s).
; ;
(define_insn "*mulsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d")
(mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
(match_operand:SI 1 "register_operand" "0")))]
""
"mh\t%0,%2"
[(set_attr "op_type" "RX")
(set_attr "type" "imul")])
(define_insn "mulsi3" (define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d") [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
...@@ -4057,37 +4065,34 @@ ...@@ -4057,37 +4065,34 @@
; mulsidi3 instruction pattern(s). ; mulsidi3 instruction pattern(s).
; ;
(define_expand "mulsidi3" (define_insn "mulsidi3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "=d,d")
(mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")) (mult:DI (sign_extend:DI
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))] (match_operand:SI 1 "register_operand" "%0,0"))
(sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
"!TARGET_64BIT" "!TARGET_64BIT"
{ "@
rtx insn; mr\t%0,%2
m\t%0,%2"
emit_insn (gen_zero_extendsidi2 (operands[0], operands[1])); [(set_attr "op_type" "RR,RX")
insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2])); (set_attr "type" "imul")])
REG_NOTES (insn) = ;
gen_rtx_EXPR_LIST (REG_EQUAL, ; umulsidi3 instruction pattern(s).
gen_rtx_MULT (DImode, ;
gen_rtx_SIGN_EXTEND (DImode, operands[1]),
gen_rtx_SIGN_EXTEND (DImode, operands[2])),
REG_NOTES (insn));
DONE;
})
(define_insn "mulsi_6432" (define_insn "umulsidi3"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(mult:DI (sign_extend:DI (mult:DI (zero_extend:DI
(truncate:SI (match_operand:DI 1 "register_operand" "0,0"))) (match_operand:SI 1 "register_operand" "%0,0"))
(sign_extend:DI (zero_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,R"))))] (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
"!TARGET_64BIT" "!TARGET_64BIT && TARGET_CPU_ZARCH"
"@ "@
mr\t%0,%2 mlr\t%0,%2
m\t%0,%2" ml\t%0,%2"
[(set_attr "op_type" "RR,RX") [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "imul")]) (set_attr "type" "imul")])
; ;
...@@ -4222,30 +4227,20 @@ ...@@ -4222,30 +4227,20 @@
(define_expand "divmoddi4" (define_expand "divmoddi4"
[(parallel [(set (match_operand:DI 0 "general_operand" "") [(parallel [(set (match_operand:DI 0 "general_operand" "")
(div:DI (match_operand:DI 1 "general_operand" "") (div:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "general_operand" ""))) (match_operand:DI 2 "general_operand" "")))
(set (match_operand:DI 3 "general_operand" "") (set (match_operand:DI 3 "general_operand" "")
(mod:DI (match_dup 1) (match_dup 2)))]) (mod:DI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))] (clobber (match_dup 4))]
"TARGET_64BIT" "TARGET_64BIT"
{ {
rtx insn, div_equal, mod_equal, equal; rtx insn, div_equal, mod_equal;
div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
equal = gen_rtx_IOR (TImode,
gen_rtx_ZERO_EXTEND (TImode, div_equal),
gen_rtx_ASHIFT (TImode,
gen_rtx_ZERO_EXTEND (TImode, mod_equal),
GEN_INT (64)));
operands[4] = gen_reg_rtx(TImode); operands[4] = gen_reg_rtx(TImode);
emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
REG_NOTES (insn) = REG_NOTES (insn) =
...@@ -4262,11 +4257,11 @@ ...@@ -4262,11 +4257,11 @@
[(set (match_operand:TI 0 "register_operand" "=d,d") [(set (match_operand:TI 0 "register_operand" "=d,d")
(ior:TI (ior:TI
(zero_extend:TI (zero_extend:TI
(div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0")) (div:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m"))) (match_operand:DI 2 "general_operand" "d,m")))
(ashift:TI (ashift:TI
(zero_extend:TI (zero_extend:TI
(mod:DI (truncate:DI (match_dup 1)) (mod:DI (match_dup 1)
(match_dup 2))) (match_dup 2)))
(const_int 64))))] (const_int 64))))]
"TARGET_64BIT" "TARGET_64BIT"
...@@ -4280,11 +4275,11 @@ ...@@ -4280,11 +4275,11 @@
[(set (match_operand:TI 0 "register_operand" "=d,d") [(set (match_operand:TI 0 "register_operand" "=d,d")
(ior:TI (ior:TI
(zero_extend:TI (zero_extend:TI
(div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0")) (div:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")))) (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
(ashift:TI (ashift:TI
(zero_extend:TI (zero_extend:TI
(mod:DI (truncate:DI (match_dup 1)) (mod:DI (match_dup 1)
(sign_extend:DI (match_dup 2)))) (sign_extend:DI (match_dup 2))))
(const_int 64))))] (const_int 64))))]
"TARGET_64BIT" "TARGET_64BIT"
...@@ -4418,13 +4413,69 @@ ...@@ -4418,13 +4413,69 @@
; udivsi3 and umodsi3 instruction pattern(s). ; udivsi3 and umodsi3 instruction pattern(s).
; ;
(define_expand "udivmodsi4"
[(parallel [(set (match_operand:SI 0 "general_operand" "")
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "nonimmediate_operand" "")))
(set (match_operand:SI 3 "general_operand" "")
(umod:SI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
"!TARGET_64BIT && TARGET_CPU_ZARCH"
{
rtx insn, div_equal, mod_equal, equal;
div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
equal = gen_rtx_IOR (DImode,
gen_rtx_ZERO_EXTEND (DImode, div_equal),
gen_rtx_ASHIFT (DImode,
gen_rtx_ZERO_EXTEND (DImode, mod_equal),
GEN_INT (32)));
operands[4] = gen_reg_rtx(DImode);
emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
DONE;
})
(define_insn "udivmoddisi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(ior:DI (zero_extend:DI
(truncate:SI
(udiv:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,m")))))
(ashift:DI
(zero_extend:DI
(truncate:SI
(umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
(const_int 32))))]
"!TARGET_64BIT && TARGET_CPU_ZARCH"
"@
dlr\t%0,%2
dl\t%0,%2"
[(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")])
(define_expand "udivsi3" (define_expand "udivsi3"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(udiv:SI (match_operand:SI 1 "general_operand" "") (udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" ""))) (match_operand:SI 2 "general_operand" "")))
(clobber (match_dup 3))] (clobber (match_dup 3))]
"!TARGET_64BIT" "!TARGET_64BIT && !TARGET_CPU_ZARCH"
{ {
rtx insn, udiv_equal, umod_equal, equal; rtx insn, udiv_equal, umod_equal, equal;
...@@ -4515,7 +4566,7 @@ ...@@ -4515,7 +4566,7 @@
(umod:SI (match_operand:SI 1 "nonimmediate_operand" "") (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "nonimmediate_operand" ""))) (match_operand:SI 2 "nonimmediate_operand" "")))
(clobber (match_dup 3))] (clobber (match_dup 3))]
"!TARGET_64BIT" "!TARGET_64BIT && !TARGET_CPU_ZARCH"
{ {
rtx insn, udiv_equal, umod_equal, equal; rtx insn, udiv_equal, umod_equal, equal;
......
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