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riscv-gcc-1
Commit f1d5187e by Richard Sandiford Committed by Richard Sandiford
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mips.c: Various formatting fixes. 

	* config/mips/mips.c: Various formatting fixes.
	(override_options): Resync -mtune handling with gas.
	(mips_issue_rate): Rearrange like mips_use_dfa_pipeline_interface.
	* config/mips/mips.h: More formatting fixes.
	(mips_abi): Move declaration.
	* config/mips/mips.md (exception_receiver): Add mode to
	unspec_volatile.

From-SVN: r70327
parent 00332c9f
Showing with 63 additions and 52 deletions
gcc/ChangeLog
2003-08-11 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.c: Various formatting fixes.
(override_options): Resync -mtune handling with gas.
(mips_issue_rate): Rearrange like mips_use_dfa_pipeline_interface.
* config/mips/mips.h: More formatting fixes.
(mips_abi): Move declaration.
* config/mips/mips.md (exception_receiver): Add mode to
unspec_volatile.
2003-08-11 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.c (spe_init_builtins): Handle evsplati and
......
gcc/config/mips/mips.c
......@@ -57,18 +57,18 @@ Boston, MA 02111-1307, USA. */
of EQ, NE, etc. */
enum internal_test {
ITEST_EQ,
ITEST_NE,
ITEST_GT,
ITEST_GE,
ITEST_LT,
ITEST_LE,
ITEST_GTU,
ITEST_GEU,
ITEST_LTU,
ITEST_LEU,
ITEST_MAX
};
ITEST_EQ,
ITEST_NE,
ITEST_GT,
ITEST_GE,
ITEST_LT,
ITEST_LE,
ITEST_GTU,
ITEST_GEU,
ITEST_LTU,
ITEST_LEU,
ITEST_MAX
};
/* Return true if it is likely that the given mode will be accessed
using only a single instruction. */
......@@ -4690,9 +4690,6 @@ override_options ()
if (mips_arch_string != 0)
mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
if (mips_tune_string != 0)
mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
if (mips_isa_string != 0)
{
/* Handle -mipsN. */
......@@ -4729,6 +4726,9 @@ override_options ()
mips_arch_info->name);
/* Optimize for mips_arch, unless -mtune selects a different processor. */
if (mips_tune_string != 0)
mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
if (mips_tune_info == 0)
mips_set_tune (mips_arch_info);
......@@ -9940,11 +9940,11 @@ mips_issue_rate ()
{
switch (mips_tune)
{
case PROCESSOR_R3000: return 1;
case PROCESSOR_R5400: return 2;
case PROCESSOR_R5500: return 2;
case PROCESSOR_R7000: return 2;
case PROCESSOR_R9000: return 2;
case PROCESSOR_R5400:
case PROCESSOR_R5500:
case PROCESSOR_R7000:
case PROCESSOR_R9000:
return 2;
default:
return 1;
......@@ -9979,30 +9979,30 @@ const char *
mips_emit_prefetch (operands)
rtx operands[];
{
/* For the mips32/64 architectures the hint fields are arranged
by operation (load/store) and locality (normal/streamed/retained).
Irritatingly, numbers 2 and 3 are reserved leaving no simple
algorithm for figuring the hint. */
/* For the mips32/64 architectures the hint fields are arranged
by operation (load/store) and locality (normal/streamed/retained).
Irritatingly, numbers 2 and 3 are reserved leaving no simple
algorithm for figuring the hint. */
int write = INTVAL (operands[1]);
int locality = INTVAL (operands[2]);
int write = INTVAL (operands[1]);
int locality = INTVAL (operands[2]);
static const char * const alt[2][4] = {
{
"pref\t4,%a0",
"pref\t0,%a0",
"pref\t0,%a0",
"pref\t6,%a0"
},
{
"pref\t5,%a0",
"pref\t1,%a0",
"pref\t1,%a0",
"pref\t7,%a0"
}
};
static const char * const alt[2][4] = {
{
"pref\t4,%a0",
"pref\t0,%a0",
"pref\t0,%a0",
"pref\t6,%a0"
},
{
"pref\t5,%a0",
"pref\t1,%a0",
"pref\t1,%a0",
"pref\t7,%a0"
}
};
return alt[write][locality];
return alt[write][locality];
}
......
gcc/config/mips/mips.h
......@@ -114,6 +114,7 @@ extern enum cmp_type branch_type; /* what type of branch to use */
extern enum processor_type mips_arch; /* which cpu to codegen for */
extern enum processor_type mips_tune; /* which cpu to schedule for */
extern int mips_isa; /* architectural level */
extern int mips_abi; /* which ABI to use */
extern int mips16_hard_float; /* mips16 without -msoft-float */
extern int mips_entry; /* generate entry/exit for mips16 */
extern const char *mips_arch_string; /* for -march=<xxx> */
......@@ -363,7 +364,7 @@ extern const struct mips_cpu_info *mips_tune_info;
/* We do this here because __mips is defined below \
and so we can't use builtin_define_std. */ \
if (!flag_iso) \
builtin_define ("mips"); \
builtin_define ("mips"); \
\
/* Treat _R3000 and _R4000 like register-size defines, \
which is how they've historically been used. */ \
......@@ -379,12 +380,12 @@ extern const struct mips_cpu_info *mips_tune_info;
builtin_define ("_R3000"); \
} \
if (TARGET_FLOAT64) \
builtin_define ("__mips_fpr=64"); \
builtin_define ("__mips_fpr=64"); \
else \
builtin_define ("__mips_fpr=32"); \
builtin_define ("__mips_fpr=32"); \
\
if (TARGET_MIPS16) \
builtin_define ("__mips16"); \
builtin_define ("__mips16"); \
\
MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
......@@ -429,12 +430,12 @@ extern const struct mips_cpu_info *mips_tune_info;
} \
\
if (TARGET_HARD_FLOAT) \
builtin_define ("__mips_hard_float"); \
builtin_define ("__mips_hard_float"); \
else if (TARGET_SOFT_FLOAT) \
builtin_define ("__mips_soft_float"); \
builtin_define ("__mips_soft_float"); \
\
if (TARGET_SINGLE_FLOAT) \
builtin_define ("__mips_single_float"); \
builtin_define ("__mips_single_float"); \
\
if (TARGET_BIG_ENDIAN) \
{ \
......@@ -976,8 +977,6 @@ extern const struct mips_cpu_info *mips_tune_info;
#define SUBTARGET_TARGET_SWITCHES
extern int mips_abi;
#ifndef MIPS_ABI_DEFAULT
#define MIPS_ABI_DEFAULT ABI_32
#endif
......@@ -1223,7 +1222,9 @@ extern int mips_abi;
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
/* Describe how we implement __builtin_eh_return. */
#define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
#define EH_RETURN_DATA_REGNO(N) \
((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
/* Offsets recorded in opcodes are a multiple of this alignment factor.
......
gcc/config/mips/mips.md
......@@ -8453,7 +8453,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
(define_insn "exception_receiver"
[(set (reg:SI 28)
(unspec_volatile [(const_int 0)] UNSPEC_EH_RECEIVER))]
(unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
"TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64)"
{ return mips_restore_gp (operands); }
[(set_attr "type" "load")
......
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