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riscv-gcc-1
Commit f1bf33ce by Uros Bizjak Committed by Uros Bizjak
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re PR target/34673 (ICE in extract_insn, at recog.c:1990) 

        PR target/34673
        * config/i386/i386.c (ix86_emit_swsqrtsf): Swap input operands
        in the call to gen_rtx_NE.  Remove unneeded VECTOR_MODE_P check.
        Update copyright year.

        * config/i386/i386.md (rsqrtsf2): Enable for TARGET_SSE_MATH.
        Update copyright year.
        * config/i386/sse.md (rsqrtv4sf2): Ditto. Unconditionally expand
        using NR fixup.

From-SVN: r131335
parent 12a6309e
Showing with 24 additions and 25 deletions
gcc/ChangeLog
2008-01-05 Uros Bizjak <ubizjak@gmail.com>
PR target/34673
* config/i386/i386.c (ix86_emit_swsqrtsf): Swap input operands
in the call to gen_rtx_NE. Remove unneeded VECTOR_MODE_P check.
Update copyright year.
* config/i386/i386.md (rsqrtsf2): Enable for TARGET_SSE_MATH.
Update copyright year.
* config/i386/sse.md (rsqrtv4sf2): Ditto. Unconditionally expand
using NR fixup.
2008-01-05 Zhouyi Zhou <zhouzhouyi@FreeBSD.org>
* tree-vrp.c (find_conditional_asserts): Remove redundant check that
gcc/config/i386/i386.c
/* Subroutines used for code generation on IA-32.
Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
2002, 2003, 2004, 2005, 2006, 2007, 2008
Free Software Foundation, Inc.
This file is part of GCC.
......@@ -24239,22 +24240,15 @@ void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
/* Compare a to zero. */
emit_insn (gen_rtx_SET (VOIDmode, mask,
gen_rtx_NE (mode, a, zero)));
gen_rtx_NE (mode, zero, a)));
/* x0 = 1./sqrt(a) estimate */
emit_insn (gen_rtx_SET (VOIDmode, x0,
gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
UNSPEC_RSQRT)));
/* Filter out infinity. */
if (VECTOR_MODE_P (mode))
emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (V4SFmode, x0),
gen_rtx_AND (mode,
gen_lowpart (V4SFmode, x0),
gen_lowpart (V4SFmode, mask))));
else
emit_insn (gen_rtx_SET (VOIDmode, x0,
gen_rtx_AND (mode, x0, mask)));
emit_insn (gen_rtx_SET (VOIDmode, x0,
gen_rtx_AND (mode, x0, mask)));
/* e0 = x0 * a */
emit_insn (gen_rtx_SET (VOIDmode, e0,
gen_rtx_MULT (mode, x0, a)));
......
gcc/config/i386/i386.md
;; GCC machine description for IA-32 and x86-64.
;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
;; 2001, 2002, 2003, 2004, 2005, 2006, 2007
;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
;; Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; x86_64 support added by Jan Hubicka
......@@ -16635,9 +16635,7 @@
[(set (match_operand:SF 0 "register_operand" "")
(unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "")]
UNSPEC_RSQRT))]
"TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
&& flag_finite_math_only && !flag_trapping_math
&& flag_unsafe_math_optimizations"
"TARGET_SSE_MATH"
{
ix86_emit_swsqrtsf (operands[0], operands[1], SFmode, 1);
DONE;
......
gcc/config/i386/sse.md
;; GCC machine description for SSE instructions
;; Copyright (C) 2005, 2006, 2007
;; Copyright (C) 2005, 2006, 2007, 2008
;; Free Software Foundation, Inc.
;;
;; This file is part of GCC.
......@@ -536,15 +536,10 @@
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF
[(match_operand:V4SF 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))]
"TARGET_SSE"
"TARGET_SSE_MATH"
{
if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
&& flag_finite_math_only && !flag_trapping_math
&& flag_unsafe_math_optimizations)
{
ix86_emit_swsqrtsf (operands[0], operands[1], V4SFmode, 1);
DONE;
}
ix86_emit_swsqrtsf (operands[0], operands[1], V4SFmode, 1);
DONE;
})
(define_insn "sse_rsqrtv4sf2"
......@@ -569,7 +564,7 @@
(set_attr "mode" "SF")])
(define_expand "sqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=")
[(set (match_operand:V4SF 0 "register_operand" "")
(sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")))]
"TARGET_SSE"
{
......
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