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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
f12c5ef3
Commit
f12c5ef3
authored
Oct 25, 1999
by
Richard Earnshaw
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* arm.md (pic_load_addr): Add constraints to operand 1.
From-SVN: r30170
parent
2ca12935
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gcc/ChangeLog
+6
-1
gcc/config/arm/arm.md
+10
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gcc/ChangeLog
View file @
f12c5ef3
Mon
Oct
25
22
:
08
:
35
1999
Richard
Earnshaw
(
rearnsha
@arm
.
com
)
*
arm
.
md
(
pic_load_addr
)
:
Add
constraints
to
operand
1
.
1999
-
10
-
25
Bruce
Korb
<
autogen
@linuxbox
.
com
>
*
fixinc
/
genfixes
:
Provide
a
means
for
specifying
-
D
options
to
AutoGen
*
fixinc
/
genfixes
:
Provide
a
means
for
specifying
-
D
options
to
AutoGen
Mon
Oct
25
00
:
42
:
35
1999
Jeffrey
A
Law
(
law
@cygnus
.
com
)
...
...
gcc/config/arm/arm.md
View file @
f12c5ef3
...
...
@@ -2858,16 +2858,20 @@
&& GET_CODE (XEXP (XEXP (operands
[
1
]
, 0), 1)) == CONST_INT))"
"adr%?
\\
t%0, %a1")
/
*
When generating pic, we need to load the symbol offset into a register.
So that the optimizer does not confuse this with a normal symbol load
we use an unspec. The offset will be loaded from a constant pool entry,
since that is the only type of relocation we can use.
*
/
;; When generating pic, we need to load the symbol offset into a register.
;; So that the optimizer does not confuse this with a normal symbol load
;; we use an unspec. The offset will be loaded from a constant pool entry,
;; since that is the only type of relocation we can use.
;; The rather odd constraints on the following are to force reload to leave
;; the insn alone, and to force the minipool generation pass to then move
;; the GOT symbol to memory.
(define_insn "pic_load_addr"
[
(set (match_operand:SI 0 "s_register_operand" "=r")
(unspec:SI
[
(match_operand
1 "" "
")
]
3))]
(unspec:SI
[
(match_operand
:SI 1 "" "mX
")
]
3))]
"flag_pic"
"ldr%?
\\
t%0, %
a
1"
"ldr%?
\\
t%0, %1"
[
(set_attr "type" "load")
(set_attr "pool_range" "4096")])
...
...
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