Commit f05911fb by Oleg Endo

sh.opt (mcbranch-force-delay-slot): New option.

gcc/
	* config/sh/sh.opt (mcbranch-force-delay-slot): New option.
	* doc/invoke.texi (SH options): Document it.
	* config/sh/sh.c (sh_insn_length_adjustment): Check
	TARGET_CBRANCH_FORCE_DELAY_SLOT instead of sh_cpu_attr == CPU_SH2E.

gcc/testsuite/
	* gcc.target/sh/sh.exp (check_effective_target_sh1): New.
	* gcc.target/sh/force-cbranch-delay-slot.c: New.

From-SVN: r220774
parent 3c99176a
2015-02-17 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/sh.opt (mcbranch-force-delay-slot): New option.
* doc/invoke.texi (SH options): Document it.
* config/sh/sh.c (sh_insn_length_adjustment): Check
TARGET_CBRANCH_FORCE_DELAY_SLOT instead of sh_cpu_attr == CPU_SH2E.
2015-02-17 H.J. Lu <hongjiu.lu@intel.com> 2015-02-17 H.J. Lu <hongjiu.lu@intel.com>
* common.opt (fipa-cp-alignment): New. * common.opt (fipa-cp-alignment): New.
......
...@@ -10245,11 +10245,10 @@ sh_insn_length_adjustment (rtx_insn *insn) ...@@ -10245,11 +10245,10 @@ sh_insn_length_adjustment (rtx_insn *insn)
&& get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES) && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
return 2; return 2;
/* SH2e has a bug that prevents the use of annulled branches, so if /* Increase the insn length of a cbranch without a delay slot insn to
the delay slot is not filled, we'll have to put a NOP in it. */ force a delay slot which will be stuffed with a nop. */
if (sh_cpu_attr == CPU_SH2E if (TARGET_CBRANCH_FORCE_DELAY_SLOT && TARGET_SH2
&& JUMP_P (insn) && JUMP_P (insn) && get_attr_type (insn) == TYPE_CBRANCH
&& get_attr_type (insn) == TYPE_CBRANCH
&& ! sequence_insn_p (insn)) && ! sequence_insn_p (insn))
return 2; return 2;
......
...@@ -229,7 +229,7 @@ Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1) ...@@ -229,7 +229,7 @@ Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1)
Cost to assume for a branch insn Cost to assume for a branch insn
mzdcbranch mzdcbranch
Target Var(TARGET_ZDCBRANCH) Target Report Var(TARGET_ZDCBRANCH)
Assume that zero displacement conditional branches are fast Assume that zero displacement conditional branches are fast
mcbranchdi mcbranchdi
...@@ -240,6 +240,10 @@ mcmpeqdi ...@@ -240,6 +240,10 @@ mcmpeqdi
Target Undocumented Var(TARGET_CMPEQDI_T) Warn(%qs is deprecated and has no effect) Target Undocumented Var(TARGET_CMPEQDI_T) Warn(%qs is deprecated and has no effect)
Emit cmpeqdi_t pattern even when -mcbranchdi is in effect. Emit cmpeqdi_t pattern even when -mcbranchdi is in effect.
mcbranch-force-delay-slot
Target Report RejectNegative Var(TARGET_CBRANCH_FORCE_DELAY_SLOT) Init(0)
Force the usage of delay slots for conditional branches.
mcut2-workaround mcut2-workaround
Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND) Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND)
Enable SH5 cut2 workaround Enable SH5 cut2 workaround
......
...@@ -965,6 +965,7 @@ See RS/6000 and PowerPC Options. ...@@ -965,6 +965,7 @@ See RS/6000 and PowerPC Options.
-maccumulate-outgoing-args -minvalid-symbols @gol -maccumulate-outgoing-args -minvalid-symbols @gol
-matomic-model=@var{atomic-model} @gol -matomic-model=@var{atomic-model} @gol
-mbranch-cost=@var{num} -mzdcbranch -mno-zdcbranch @gol -mbranch-cost=@var{num} -mzdcbranch -mno-zdcbranch @gol
-mcbranch-force-delay-slot @gol
-mfused-madd -mno-fused-madd -mfsca -mno-fsca -mfsrra -mno-fsrra @gol -mfused-madd -mno-fused-madd -mfsca -mno-fsca -mfsrra -mno-fsrra @gol
-mpretend-cmove -mtas} -mpretend-cmove -mtas}
...@@ -20593,6 +20594,13 @@ compiler prefers zero displacement branch code sequences. This is ...@@ -20593,6 +20594,13 @@ compiler prefers zero displacement branch code sequences. This is
enabled by default when generating code for SH4 and SH4A. It can be explicitly enabled by default when generating code for SH4 and SH4A. It can be explicitly
disabled by specifying @option{-mno-zdcbranch}. disabled by specifying @option{-mno-zdcbranch}.
@item -mcbranch-force-delay-slot
@opindex mcbranch-force-delay-slot
Force the usage of delay slots for conditional branches, which stuffs the delay
slot with a @code{nop} if a suitable instruction can't be found. By default
this option is disabled. It can be enabled to work around hardware bugs as
found in the original SH7055.
@item -mfused-madd @item -mfused-madd
@itemx -mno-fused-madd @itemx -mno-fused-madd
@opindex mfused-madd @opindex mfused-madd
......
2015-02-17 Oleg Endo <olegendo@gcc.gnu.org>
* gcc.target/sh/sh.exp (check_effective_target_sh1): New.
* gcc.target/sh/force-cbranch-delay-slot.c: New.
2015-02-17 H.J. Lu <hongjiu.lu@intel.com> 2015-02-17 H.J. Lu <hongjiu.lu@intel.com>
* gcc.dg/ipa/propalign-3.c: New test. * gcc.dg/ipa/propalign-3.c: New test.
......
/* Check that the option -mcbranch-force-delay-slot works as expected on
targets other than SH1, and that it compiles on SH1 targets without fuzz. */
/* { dg-do compile } */
/* { dg-options "-O2 -mcbranch-force-delay-slot" } */
/* { dg-final { scan-assembler-times "nop" 2 { target { ! sh1 } } } } */
int g (int, int);
int
f (int a, int b)
{
/* Expected: 1x bt/s, 1x nop. */
if (a != 5)
a = 10;
/* Expected: 1x jmp, 1x nop. */
return g (a, b);
}
...@@ -33,6 +33,15 @@ proc check_effective_target_sh2a { } { ...@@ -33,6 +33,15 @@ proc check_effective_target_sh2a { } {
} ""] } ""]
} }
# Return 1 if target is SH1
proc check_effective_target_sh1 { } {
return [check_no_compiler_messages sh1 object {
#ifndef __SH1__
#error ""
#endif
} ""]
}
# Return 1 if target supports atomic-model=soft-gusa # Return 1 if target supports atomic-model=soft-gusa
proc check_effective_target_atomic_model_soft_gusa_available { } { proc check_effective_target_atomic_model_soft_gusa_available { } {
return [check_no_compiler_messages atomic_model_soft_gusa_available object { return [check_no_compiler_messages atomic_model_soft_gusa_available object {
......
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