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Commit ef22810a by Richard Henderson Committed by Richard Henderson
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re PR target/69305 (wrong code with -O and int128 @ aarch64) 

PR target/69305

  * config/aarch64/aarch64-modes.def (CC_Cmode): New
  * config/aarch64/aarch64-protos.h: Update.
  * config/aarch64/aarch64.c (aarch64_zero_extend_const_eq): New.
  (aarch64_select_cc_mode): Add check for use of CC_Cmode.
  (aarch64_get_condition_code_1): Handle CC_Cmode.
  * config/aarch64/aarch64.md (addti3): Use adddi3_compareC.
  (*add<mode>3_compareC_cconly_imm): New.
  (*add<mode>3_compareC_cconly): New.
  (*add<mode>3_compareC_imm): New.
  (add<mode>3_compareC): New.
  (add<mode>3_carryin, *addsi3_carryin_uxtw): Sort compare operand
  to be first.  Use aarch64_carry_operation.
  (*add<mode>3_carryin_alt1, *addsi3_carryin_alt1_uxtw): Remove.
  (*add<mode>3_carryin_alt2, *addsi3_carryin_alt2_uxtw): Remove.
  (*add<mode>3_carryin_alt3, *addsi3_carryin_alt3_uxtw): Remove.
  (subti3): Use subdi3_compare1.
  (*sub<mode>3_compare0): Rename from sub<mode>3_compare0.
  (sub<mode>3_compare1): New.
  (*sub<mode>3_carryin0, *subsi3_carryin_uxtw): New.
  (*sub<mode>3_carryin): Use aarch64_borrow_operation.
  (*subsi3_carryin_uxtw): Likewise.
  (*ngc<mode>, *ngcsi_uxtw): Likewise.
  (*sub<mode>3_carryin_alt, *subsi3_carryin_alt_uxtw): New.
  * config/aarch64/iterators.md (DWI): New.
  * config/aarch64/predicates.md (aarch64_carry_operation): New.
  (aarch64_borrow_operation): New.

From-SVN: r232936
parent 8d18bd10
Showing with 82 additions and 2 deletions
gcc/ChangeLog
2016-01-28 Richard Henderson <rth@redhat.com>
PR target/69305
* config/aarch64/aarch64-modes.def (CC_Cmode): New
* config/aarch64/aarch64-protos.h: Update.
* config/aarch64/aarch64.c (aarch64_zero_extend_const_eq): New.
(aarch64_select_cc_mode): Add check for use of CC_Cmode.
(aarch64_get_condition_code_1): Handle CC_Cmode.
* config/aarch64/aarch64.md (addti3): Use adddi3_compareC.
(*add<mode>3_compareC_cconly_imm): New.
(*add<mode>3_compareC_cconly): New.
(*add<mode>3_compareC_imm): New.
(add<mode>3_compareC): New.
(add<mode>3_carryin, *addsi3_carryin_uxtw): Sort compare operand
to be first. Use aarch64_carry_operation.
(*add<mode>3_carryin_alt1, *addsi3_carryin_alt1_uxtw): Remove.
(*add<mode>3_carryin_alt2, *addsi3_carryin_alt2_uxtw): Remove.
(*add<mode>3_carryin_alt3, *addsi3_carryin_alt3_uxtw): Remove.
(subti3): Use subdi3_compare1.
(*sub<mode>3_compare0): Rename from sub<mode>3_compare0.
(sub<mode>3_compare1): New.
(*sub<mode>3_carryin0, *subsi3_carryin_uxtw): New.
(*sub<mode>3_carryin): Use aarch64_borrow_operation.
(*subsi3_carryin_uxtw): Likewise.
(*ngc<mode>, *ngcsi_uxtw): Likewise.
(*sub<mode>3_carryin_alt, *subsi3_carryin_alt_uxtw): New.
* config/aarch64/iterators.md (DWI): New.
* config/aarch64/predicates.md (aarch64_carry_operation): New.
(aarch64_borrow_operation): New.
2016-01-28 Abderrazek Zaafrani <a.zaafrani@samsung.com>
* graphite-optimize-isl.c (optimize_isl): Print a different debug
......
gcc/config/aarch64/aarch64-modes.def
......@@ -25,6 +25,7 @@ CC_MODE (CC_ZESWP); /* zero-extend LHS (but swap to make it RHS). */
CC_MODE (CC_SESWP); /* sign-extend LHS (but swap to make it RHS). */
CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */
CC_MODE (CC_Z); /* Only Z bit of condition flags is valid. */
CC_MODE (CC_C); /* Only C bit of condition flags is valid. */
/* Half-precision floating point for __fp16. */
FLOAT_MODE (HF, 2, 0);
......
gcc/config/aarch64/aarch64-protos.h
......@@ -290,6 +290,7 @@ void aarch64_declare_function_name (FILE *, const char*, tree);
bool aarch64_legitimate_pic_operand_p (rtx);
bool aarch64_modes_tieable_p (machine_mode mode1,
machine_mode mode2);
bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx);
bool aarch64_move_imm (HOST_WIDE_INT, machine_mode);
bool aarch64_mov_operand_p (rtx, machine_mode);
int aarch64_simd_attr_length_rglist (enum machine_mode);
......
gcc/config/aarch64/aarch64.c
......@@ -1493,6 +1493,16 @@ aarch64_split_simd_move (rtx dst, rtx src)
}
}
bool
aarch64_zero_extend_const_eq (machine_mode xmode, rtx x,
machine_mode ymode, rtx y)
{
rtx r = simplify_const_unary_operation (ZERO_EXTEND, xmode, y, ymode);
gcc_assert (r != NULL);
return rtx_equal_p (x, r);
}
static rtx
aarch64_force_temporary (machine_mode mode, rtx x, rtx value)
{
......@@ -4189,6 +4199,13 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
return ((code == GT || code == GE || code == LE || code == LT)
? CC_SESWPmode : CC_ZESWPmode);
/* A test for unsigned overflow. */
if ((GET_MODE (x) == DImode || GET_MODE (x) == TImode)
&& code == NE
&& GET_CODE (x) == PLUS
&& GET_CODE (y) == ZERO_EXTEND)
return CC_Cmode;
/* For everything else, return CCmode. */
return CCmode;
}
......@@ -4288,6 +4305,15 @@ aarch64_get_condition_code_1 (enum machine_mode mode, enum rtx_code comp_code)
}
break;
case CC_Cmode:
switch (comp_code)
{
case NE: return AARCH64_CS;
case EQ: return AARCH64_CC;
default: return -1;
}
break;
default:
return -1;
break;
......
gcc/config/aarch64/iterators.md
......@@ -350,6 +350,9 @@
;; For constraints used in scalar immediate vector moves
(define_mode_attr hq [(HI "h") (QI "q")])
;; For doubling width of an integer mode
(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
;; For scalar usage of vector/FP registers
(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
(SF "s") (DF "d")
......
gcc/config/aarch64/predicates.md
......@@ -242,6 +242,25 @@
return aarch64_get_condition_code (op) >= 0;
})
(define_special_predicate "aarch64_carry_operation"
(match_code "ne,geu")
{
if (XEXP (op, 1) != const0_rtx)
return false;
machine_mode ccmode = (GET_CODE (op) == NE ? CC_Cmode : CCmode);
rtx op0 = XEXP (op, 0);
return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
})
(define_special_predicate "aarch64_borrow_operation"
(match_code "eq,ltu")
{
if (XEXP (op, 1) != const0_rtx)
return false;
machine_mode ccmode = (GET_CODE (op) == EQ ? CC_Cmode : CCmode);
rtx op0 = XEXP (op, 0);
return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
})
;; True if the operand is memory reference suitable for a load/store exclusive.
(define_predicate "aarch64_sync_memory_operand"
......
gcc/testsuite/gcc.target/aarch64/ccmp_1.c
......@@ -85,7 +85,7 @@ f13 (int a, int b)
/* { dg-final { scan-assembler "cmp\t(.)+34" } } */
/* { dg-final { scan-assembler "cmp\t(.)+35" } } */
/* { dg-final { scan-assembler-times "\tcmp\tw\[0-9\]+, 0" 4 } } */
/* { dg-final { scan-assembler-times "\tcmp\tw\[0-9\]+, (0|wzr)" 4 } } */
/* { dg-final { scan-assembler-times "fcmpe\t(.)+0\\.0" 2 } } */
/* { dg-final { scan-assembler-times "fcmp\t(.)+0\\.0" 2 } } */
......
gcc/testsuite/gcc.target/aarch64/tst_3.c
......@@ -9,4 +9,4 @@ f1 (int x)
return x;
}
/* { dg-final { scan-assembler "tst\t(x|w)\[0-9\]*.*1" } } */
/* { dg-final { scan-assembler "(tst|ands)\t(x|w)\[0-9\]*.*1" } } */
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