2018-05-15 Michael Collison <michael.collison@arm.com>

	* config/aarch64/aarch64.md:
	(*fix_to_zero_extenddfdi2): New pattern.
	* gcc.target/aarch64/fix_extend1.c: New testcase.

From-SVN: r261051

gcc/ChangeLog

+2018-05-31  Michael Collison  <michael.collison@arm.com>
+
+	* config/aarch64/aarch64.md:
+	(*fix_to_zero_extenddfdi2): New pattern.
+	* gcc.target/aarch64/fix_extend1.c: New testcase.
+
 2018-05-31  Qing Zhao <qing.zhao@oracle.com>
 
 	PR middle-end/78809

gcc/config/aarch64/aarch64.md

@@ -5103,6 +5103,16 @@
   [(set_attr "type" "f_cvtf2i")]
 )
 
+(define_insn "*fix_to_zero_extend<mode>di2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI
+	 (unsigned_fix:SI
+	  (match_operand:GPF 1 "register_operand" "w"))))]
+  "TARGET_FLOAT"
+  "fcvtzu\t%w0, %<s>1"
+  [(set_attr "type" "f_cvtf2i")]
+)
+
 (define_insn "<optab><fcvt_target><GPF:mode>2"
   [(set (match_operand:GPF 0 "register_operand" "=w,w")
         (FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,?r")))]

gcc/testsuite/gcc.target/aarch64/fix_extend1.c

+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned long
+f7 (double x)
+{
+  return (unsigned) x;
+}
+
+unsigned long
+f7_2 (float x)
+{
+  return (unsigned) x;
+}
+
+/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, s\[0-9\]+" } } */