fold-vec-madd-double.c: New.

[gcc/testsuite]

2017-08-09  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-madd-double.c: New.
	* gcc.target/powerpc/fold-vec-madd-float.c: New.
	* gcc.target/powerpc/fold-vec-madd-short.c: New.

From-SVN: r250996

gcc/testsuite/ChangeLog

 2017-08-09  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
+	* gcc.target/powerpc/fold-vec-madd-double.c: New.
+	* gcc.target/powerpc/fold-vec-madd-float.c: New.
+	* gcc.target/powerpc/fold-vec-madd-short.c: New.
+
+2017-08-09  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
 	* gcc.target/powerpc/fold-vec-cntlz-int.c: New.
 	* gcc.target/powerpc/fold-vec-cntlz-char.c: New.
 	* gcc.target/powerpc/fold-vec-cntlz-short.c: New.

gcc/testsuite/gcc.target/powerpc/fold-vec-madd-double.c

+/* Verify that overloaded built-ins for vec_madd with
+   double inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+#include <altivec.h>
+
+vector double
+testd_l (vector double vd2, vector double vd3, vector double vd4)
+{
+  return vec_madd (vd2, vd3, vd4);
+}
+
+/* { dg-final { scan-assembler-times "xvmaddmdp|xvmaddadp" 1 } } */
+

gcc/testsuite/gcc.target/powerpc/fold-vec-madd-float.c

+/* Verify that overloaded built-ins for vec_madd with float
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+#include <altivec.h>
+
+vector float
+testf_l (vector float vf2, vector float vf3, vector float vf4)
+{
+  return vec_madd (vf2, vf3, vf4);
+}
+
+/* { dg-final { scan-assembler-times "xvmaddmsp|xvmaddasp" 1 } } */
+

gcc/testsuite/gcc.target/powerpc/fold-vec-madd-short.c

+/* Verify that overloaded built-ins for vec_madd with short
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed short
+test_mad_sss (vector signed short vss2, vector signed short vss3,
+	      vector signed short vss4)
+{
+  return vec_madd (vss2, vss3, vss4);
+}
+
+vector signed short
+test_mad_suu (vector signed short vss2, vector unsigned short vus3,
+		vector unsigned short vus4)
+{
+  return vec_madd (vss2, vus3, vus4);
+}
+
+vector signed short
+test_mad_uss (vector unsigned short vus2, vector signed short vss3,
+	      vector signed short vss4)
+{
+  return vec_madd (vus2, vss3, vss4);
+}
+
+vector unsigned short
+test_mad_uuu (vector unsigned short vus2, vector unsigned short vus3,
+		vector unsigned short vus4)
+{
+  return vec_madd (vus2, vus3, vus4);
+}
+
+/* { dg-final { scan-assembler-times "vmladduhm" 4 } } */