Commit ee8c0889 by Michael Meissner Committed by Michael Meissner

re PR target/65569 (Fix for PR target/65240 causes a regression in building Spec…

re PR target/65569 (Fix for PR target/65240 causes a regression in building Spec for power4/power5/power6)

2015-03-25  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/65569
	* config/rs6000/rs6000.md (extenddftf2_fprs): On VSX systems use
	XXLXOR to create 0.0.  On pre-VSX systems make sure the constant
	0.0 is correctly setup.
	(extenddftf2_internal): Likewise.

From-SVN: r221683
parent 9c5b1bf7
2015-03-25 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/65569
* config/rs6000/rs6000.md (extenddftf2_fprs): On VSX systems use
XXLXOR to create 0.0. On pre-VSX systems make sure the constant
0.0 is correctly setup.
(extenddftf2_internal): Likewise.
2015-03-25 Sebastian Pop <s.pop@samsung.com> 2015-03-25 Sebastian Pop <s.pop@samsung.com>
PR tree-optimization/65177 PR tree-optimization/65177
......
...@@ -8357,16 +8357,21 @@ ...@@ -8357,16 +8357,21 @@
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& TARGET_LONG_DOUBLE_128" && TARGET_LONG_DOUBLE_128"
{ {
operands[2] = CONST0_RTX (DFmode); /* VSX can create 0.0 directly, otherwise let rs6000_emit_move create
/* Generate GOT reference early for SVR4 PIC. */ the proper constant. */
if (DEFAULT_ABI == ABI_V4 && flag_pic) if (TARGET_VSX)
operands[2] = validize_mem (force_const_mem (DFmode, operands[2])); operands[2] = CONST0_RTX (DFmode);
else
{
operands[2] = gen_reg_rtx (DFmode);
rs6000_emit_move (operands[2], CONST0_RTX (DFmode), DFmode);
}
}) })
(define_insn_and_split "*extenddftf2_internal" (define_insn_and_split "*extenddftf2_internal"
[(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r") [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,ws,d,&d,r")
(float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rm"))) (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,md,rm")))
(use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))] (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,j,m,d,n"))]
"!TARGET_IEEEQUAD "!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& TARGET_LONG_DOUBLE_128" && TARGET_LONG_DOUBLE_128"
......
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