arm.c (load_multiple_sequence, [...]): Fix spelling in two comments.

2013-04-19  Greta Yorsh  <Greta.Yorsh@arm.com>

	* config/arm/arm.c (load_multiple_sequence, ldm_stm_operation_p): Fix
	spelling in two comments.

From-SVN: r198093

gcc/ChangeLog

 2013-04-19  Greta Yorsh  <Greta.Yorsh@arm.com>
 
+	* config/arm/arm.c (load_multiple_sequence, ldm_stm_operation_p): Fix
+	spelling in two comments.
+
+2013-04-19  Greta Yorsh  <Greta.Yorsh@arm.com>
+
 	PR target/56797
 	* config/arm/arm.c (load_multiple_sequence): Require SP
 	as base register for loads if SP is in the register list.

gcc/config/arm/arm.c

@@ -10491,7 +10491,7 @@ ldm_stm_operation_p (rtx op, bool load, enum machine_mode mode,
 
   /* Don't allow SP to be loaded unless it is also the base register. It
      guarantees that SP is reset correctly when an LDM instruction
-     is interruptted. Otherwise, we might end up with a corrupt stack.  */
+     is interrupted. Otherwise, we might end up with a corrupt stack.  */
   if (load && (REGNO (reg) == SP_REGNUM) && (REGNO (addr) != SP_REGNUM))
     return false;
 
@@ -10757,7 +10757,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order,
 
           /* Don't allow SP to be loaded unless it is also the base
              register.  It guarantees that SP is reset correctly when
-             an LDM instruction is interruptted.  Otherwise, we might
+             an LDM instruction is interrupted.  Otherwise, we might
              end up with a corrupt stack.  */
           if (unsorted_regs[i] == SP_REGNUM && base_reg != SP_REGNUM)
             return 0;