re PR middle-end/7796 (sparc-sun-solaris2.7 extra failure w/-m64 on execute/930921-1.c in unroll.c)

	PR middle-end/7796
	* unroll.c (calculate_giv_inc): Handle constants being
	loaded with LSHIFTRT.

From-SVN: r63971

gcc/ChangeLog

+2003-03-08  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	PR middle-end/7796
+	* unroll.c (calculate_giv_inc): Handle constants being
+	loaded with LSHIFTRT.
+
 2003-03-07  David Edelsohn  <edelsohn@gnu.org>
 
 	* config/rs6000/rs6000.c (processor_target_table): Do not disable
@@ -20,7 +26,7 @@
 
 2003-03-07  James E Wilson  <wilson@tuliptree.org>
 
-        * config/sh/sh.h (HARD_REGNO_NREGS): Round up the XD register count.
+	* config/sh/sh.h (HARD_REGNO_NREGS): Round up the XD register count.
 
 2003-03-07  Geoffrey Keating  <geoffk@apple.com>
 

gcc/unroll.c

@@ -1624,11 +1624,13 @@ calculate_giv_inc (pattern, src_insn, regno)
 	}
 
       else if (GET_CODE (increment) == IOR
+	       || GET_CODE (increment) == PLUS
 	       || GET_CODE (increment) == ASHIFT
-	       || GET_CODE (increment) == PLUS)
+	       || GET_CODE (increment) == LSHIFTRT)
 	{
 	  /* The rs6000 port loads some constants with IOR.
-	     The alpha port loads some constants with ASHIFT and PLUS.  */
+	     The alpha port loads some constants with ASHIFT and PLUS.
+	     The sparc64 port loads some constants with LSHIFTRT.  */
 	  rtx second_part = XEXP (increment, 1);
 	  enum rtx_code code = GET_CODE (increment);
 
@@ -1645,8 +1647,10 @@ calculate_giv_inc (pattern, src_insn, regno)
 	    increment = GEN_INT (INTVAL (increment) | INTVAL (second_part));
 	  else if (code == PLUS)
 	    increment = GEN_INT (INTVAL (increment) + INTVAL (second_part));
-	  else
+	  else if (code == ASHIFT)
 	    increment = GEN_INT (INTVAL (increment) << INTVAL (second_part));
+	  else
+	    increment = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (increment) >> INTVAL (second_part));
 	}
 
       if (GET_CODE (increment) != CONST_INT)