rs6000.h (enum processor_type): Add support for 7400 (G4) and 7450.

2001-10-01  Dale Johannesen  <dalej@apple.com>

        * config/rs6000/rs6000.h (enum processor_type): Add support
        for 7400 (G4) and 7450.
        (RTX_COSTS): Ditto.
        * config/rs6000/rs6000.c (rs6000_override_options): Ditto.
        (rs6000_issue_rate): Ditto.
        (rs6000_adjust_cost): Fix cycle counts for compares.
        (debug_stack_info):  Fix an obvious typo.
        * config/rs6000/rs6000.md: Add functional units for 7400 and 7450.
        * doc/invoke.texi: Document.
        * config/rs6000/darwin.h (TARGET_DEFAULT): Set to be reasonable
        for Darwin.
        (PROCESSOR_DEFAULT): Ditto.

From-SVN: r45937

gcc/ChangeLog

+2001-10-01  Dale Johannesen  <dalej@apple.com>
+
+	* config/rs6000/rs6000.h (enum processor_type): Add support
+	for 7400 (G4) and 7450.
+	(RTX_COSTS): Ditto.
+	* config/rs6000/rs6000.c (rs6000_override_options): Ditto.
+	(rs6000_issue_rate): Ditto.
+	(rs6000_adjust_cost): Fix cycle counts for compares.
+	(debug_stack_info):  Fix an obvious typo.
+	* config/rs6000/rs6000.md: Add functional units for 7400 and 7450.
+	* doc/invoke.texi: Document.
+	* config/rs6000/darwin.h (TARGET_DEFAULT): Set to be reasonable
+	for Darwin.
+	(PROCESSOR_DEFAULT): Ditto.
+
 2001-10-01  Loren J. Rittle  <ljrittle@acm.org>
 
 	* Makefile.in (STAGE2_FLAGS_TO_PASS): Propagate HOST_CC.

gcc/config/rs6000/darwin.h

@@ -43,10 +43,6 @@ Boston, MA 02111-1307, USA.  */
 #define FIXED_R2 0
 #define FIXED_R13 0
 
-#undef  TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_POWERPC | MASK_MULTIPLE | MASK_NEW_MNEMONICS \
-  | MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC)
-
 /* Base register for access to local variables of the function.  */
 
 #undef  FRAME_POINTER_REGNUM
@@ -146,6 +142,19 @@ Boston, MA 02111-1307, USA.  */
 
 #define RS6000_MCOUNT "*mcount"
 
+/* Default processor: a G4.  */
+
+#undef PROCESSOR_DEFAULT
+#define PROCESSOR_DEFAULT  PROCESSOR_PPC7400
+
+/* Default target flag settings.  Despite the fact that STMW/LMW
+   serializes, it's still a big codesize win to use them.  Use FSEL by
+   default as well.  */
+
+#undef  TARGET_DEFAULT
+#define TARGET_DEFAULT (MASK_POWERPC | MASK_MULTIPLE | MASK_NEW_MNEMONICS \
+                      | MASK_PPC_GFXOPT)
+
 /* Since Darwin doesn't do TOCs, stub this out.  */
 
 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY_P(X, MODE)  0

gcc/config/rs6000/rs6000.c

@@ -309,6 +309,12 @@ rs6000_override_options (default_cpu)
 	 {"750", PROCESSOR_PPC750,
  	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
  	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
+       {"7400", PROCESSOR_PPC7400,
+          MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+          POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
+       {"7450", PROCESSOR_PPC7450,
+          MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+          POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
 	 {"801", PROCESSOR_MPCCORE,
 	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
 	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
@@ -5654,7 +5660,7 @@ debug_stack_info (info)
     fprintf (stderr, "\tfp_size             = %5d\n", info->fp_size);
 
  if (info->lr_size)
-    fprintf (stderr, "\tlr_size             = %5d\n", info->cr_size);
+    fprintf (stderr, "\tlr_size             = %5d\n", info->lr_size);
 
   if (info->cr_size)
     fprintf (stderr, "\tcr_size             = %5d\n", info->cr_size);
@@ -7964,16 +7970,33 @@ rs6000_adjust_cost (insn, link, dep_insn, cost)
 
   if (REG_NOTE_KIND (link) == 0)
     {
-      /* Data dependency; DEP_INSN writes a register that INSN reads some
-	 cycles later.  */
-
-      /* Tell the first scheduling pass about the latency between a mtctr
-	 and bctr (and mtlr and br/blr).  The first scheduling pass will not
-	 know about this latency since the mtctr instruction, which has the
-	 latency associated to it, will be generated by reload.  */
-      if (get_attr_type (insn) == TYPE_JMPREG)
-	return TARGET_POWER ? 5 : 4;
-
+      /* Data dependency; DEP_INSN writes a register that INSN reads
+	 some cycles later.  */
+      switch (get_attr_type (insn))
+	{
+	case TYPE_JMPREG:
+          /* Tell the first scheduling pass about the latency between
+	     a mtctr and bctr (and mtlr and br/blr).  The first
+	     scheduling pass will not know about this latency since
+	     the mtctr instruction, which has the latency associated
+	     to it, will be generated by reload.  */
+          return TARGET_POWER ? 5 : 4;
+	case TYPE_BRANCH:
+	  /* Leave some extra cycles between a compare and its
+	     dependent branch, to inhibit expensive mispredicts.  */
+	  if ((rs6000_cpu_attr == CPU_PPC750
+               || rs6000_cpu_attr == CPU_PPC7400
+               || rs6000_cpu_attr == CPU_PPC7450)
+	      && recog_memoized (dep_insn)
+	      && (INSN_CODE (dep_insn) >= 0)
+	      && (get_attr_type (dep_insn) == TYPE_COMPARE
+		  || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
+		  || get_attr_type (dep_insn) == TYPE_FPCOMPARE
+		  || get_attr_type (dep_insn) == TYPE_CR_LOGICAL))
+	    return cost + 2;
+	default:
+	  break;
+	}
       /* Fall out to return default cost.  */
     }
 
@@ -8031,9 +8054,11 @@ rs6000_issue_rate ()
   case CPU_RIOS1:  /* ? */
   case CPU_RS64A:
   case CPU_PPC601: /* ? */
+  case CPU_PPC7450:
     return 3;
   case CPU_PPC603:
   case CPU_PPC750:
+  case CPU_PPC7400:
     return 2; 
   case CPU_RIOS2:
   case CPU_PPC604:

gcc/config/rs6000/rs6000.h

@@ -358,7 +358,9 @@ enum processor_type
    PROCESSOR_PPC604e,
    PROCESSOR_PPC620,
    PROCESSOR_PPC630,
-   PROCESSOR_PPC750
+   PROCESSOR_PPC750,
+   PROCESSOR_PPC7400,
+   PROCESSOR_PPC7450
 };
 
 extern enum processor_type rs6000_cpu;
@@ -2116,6 +2118,8 @@ do {									     \
         return COSTS_N_INSNS (2);					\
       case PROCESSOR_PPC601:						\
         return COSTS_N_INSNS (5);					\
+      case PROCESSOR_PPC7400:                                         \
+      case PROCESSOR_PPC7450:                                         \
       case PROCESSOR_PPC603:						\
       case PROCESSOR_PPC750:						\
         return (GET_CODE (XEXP (X, 1)) != CONST_INT			\
@@ -2168,7 +2172,10 @@ do {									     \
 		? COSTS_N_INSNS (21)					\
 		: COSTS_N_INSNS (37));					\
       case PROCESSOR_PPC750:						\
+      case PROCESSOR_PPC7400:						\
         return COSTS_N_INSNS (19);					\
+      case PROCESSOR_PPC7450:						\
+        return COSTS_N_INSNS (23);					\
       }									\
   case FFS:								\
     return COSTS_N_INSNS (4);						\

gcc/config/rs6000/rs6000.md

@@ -56,7 +56,7 @@
 ;; Processor type -- this attribute must exactly match the processor_type
 ;; enumeration in rs6000.h.
 
-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"
+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450"
   (const (symbol_ref "rs6000_cpu_attr")))
 
 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
@@ -66,21 +66,46 @@
 ; (POWER and 601 use Integer Unit)
 (define_function_unit "lsu" 1 0
   (and (eq_attr "type" "load")
-       (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
+       (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400"))
   2 1)
 
 (define_function_unit "lsu" 1 0
+  (and (eq_attr "type" "load")
+       (eq_attr "cpu" "ppc7450"))
+  3 1)
+
+(define_function_unit "lsu" 1 0
   (and (eq_attr "type" "store,fpstore")
-       (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
+       (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630"))
   1 1)
 
 (define_function_unit "lsu" 1 0
+  (and (eq_attr "type" "store,fpstore")
+       (eq_attr "cpu" "ppc750,ppc7400"))
+  2 1)
+
+(define_function_unit "lsu" 1 0
+  (and (eq_attr "type" "store")
+       (eq_attr "cpu" "ppc7450"))
+  3 1)
+
+(define_function_unit "lsu" 1 0
+  (and (eq_attr "type" "fpstore")
+       (eq_attr "cpu" "ppc7450"))
+  3 3)
+
+(define_function_unit "lsu" 1 0
   (and (eq_attr "type" "fpload")
-       (eq_attr "cpu" "mpccore,ppc603,ppc750"))
+       (eq_attr "cpu" "mpccore,ppc603,ppc750,ppc7400"))
   2 1)
 
 (define_function_unit "lsu" 1 0
   (and (eq_attr "type" "fpload")
+       (eq_attr "cpu" "ppc7450"))
+  4 1)
+
+(define_function_unit "lsu" 1 0
+  (and (eq_attr "type" "fpload")
        (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630"))
   3 1)
 
@@ -270,6 +295,29 @@
        (eq_attr "cpu" "ppc620,ppc630"))
   37 36)
 
+; PPC7450 has 3 integer units (for most integer insns) and one mul/div
+; unit, which also does CR-logical insns and move to/from SPR.
+
+(define_function_unit "iu3" 3 0
+  (and (eq_attr "type" "integer")
+       (eq_attr "cpu" "ppc7450"))
+  1 1)
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "imul")
+       (eq_attr "cpu" "ppc7450"))
+  4 4)
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "idiv")
+       (eq_attr "cpu" "ppc7450"))
+  23 23)
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "cr_logical")
+       (eq_attr "cpu" "ppc7450"))
+  1 1)
+
 ; PPC750 has two integer units: a primary one which can perform all
 ; operations and a secondary one which is fed in lock step with the first
 ; and can perform "simple" integer operations.  
@@ -277,22 +325,27 @@
 ; for the complex insns. 
 (define_function_unit "iu2" 2 0
   (and (eq_attr "type" "integer")
-       (eq_attr "cpu" "ppc750"))
+       (eq_attr "cpu" "ppc750,ppc7400"))
   1 1)
 
 (define_function_unit "iu2" 2 0
   (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "ppc750"))
-  4 2)
+       (eq_attr "cpu" "ppc750,ppc7400"))
+  4 4)
+
+(define_function_unit "iu2" 2 0
+  (and (eq_attr "type" "idiv")
+       (eq_attr "cpu" "ppc750,ppc7400"))
+  19 19)
 
 (define_function_unit "imuldiv" 1 0
   (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "ppc750"))
-  4 2)
+       (eq_attr "cpu" "ppc750,ppc7400"))
+  4 4)
 
 (define_function_unit "imuldiv" 1 0
   (and (eq_attr "type" "idiv")
-       (eq_attr "cpu" "ppc750"))
+       (eq_attr "cpu" "ppc750,ppc7400"))
   19 19)
 
 ; CR-logical operations are execute-serialized, that is they don't
@@ -301,7 +354,7 @@
 ; I've imitated this by giving them longer latency.
 (define_function_unit "sru" 1 0 
   (and (eq_attr "type" "cr_logical")
-       (eq_attr "cpu" "ppc603,ppc750"))
+       (eq_attr "cpu" "ppc603,ppc750,ppc7400"))
   3 2)
 
 ; compare is done on integer unit, but feeds insns which
@@ -318,9 +371,21 @@
 
 (define_function_unit "iu" 1 0
   (and (eq_attr "type" "compare,delayed_compare")
-       (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
+       (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
   3 1)
 
+; some extra cycles added by TARGET_SCHED_ADJUST_COST between compare
+; and a following branch, to reduce mispredicts
+(define_function_unit "iu" 1 0
+  (and (eq_attr "type" "compare,delayed_compare")
+       (eq_attr "cpu" "ppc750,ppc7400"))
+  1 1)
+
+(define_function_unit "iu3" 3 0
+  (and (eq_attr "type" "compare,delayed_compare")
+       (eq_attr "cpu" "ppc7450"))
+  1 1)
+
 (define_function_unit "iu2" 2 0   
   (and (eq_attr "type" "compare,delayed_compare")
        (eq_attr "cpu" "rios2"))
@@ -328,7 +393,7 @@
 
 (define_function_unit "iu2" 2 0
   (and (eq_attr "type" "compare,delayed_compare")
-       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750"))
+       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400"))
   1 1)
 
 ; fp compare uses fp unit
@@ -355,11 +420,16 @@
 ; fp compare uses fp unit
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "fpcompare")
-       (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
+       (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
   5 1)
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "fpcompare")
+       (eq_attr "cpu"  "ppc750,ppc7400,ppc7450"))
+  3 1)
+
+(define_function_unit "fpu" 1 0
+  (and (eq_attr "type" "fpcompare")
        (eq_attr "cpu" "mpccore"))
   1 1)
 
@@ -370,7 +440,7 @@
 
 (define_function_unit "bpu" 1 0
   (and (eq_attr "type" "mtjmpr")
-       (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
+       (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450"))
   4 1)
 
 (define_function_unit "bpu" 1 0
@@ -410,10 +480,15 @@
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "fp")
-       (eq_attr "cpu" "ppc603,ppc750,ppc604,ppc604e,ppc620"))
+       (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750,ppc7400"))
   3 1)
 
 (define_function_unit "fpu" 1 0
+  (and (eq_attr "type" "fp,dmul")
+       (eq_attr "cpu" "ppc7450"))
+  5 1)
+
+(define_function_unit "fpu" 1 0
   (and (eq_attr "type" "dmul")
        (eq_attr "cpu" "rs64a"))
   7 2)
@@ -436,7 +511,7 @@
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "dmul")
-       (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
+       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc7400"))
   3 1)
 
 (define_function_unit "fpu" 1 0
@@ -451,11 +526,16 @@
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "sdiv")
-       (eq_attr "cpu" "ppc601"))
+       (eq_attr "cpu" "ppc601,ppc750,ppc7400"))
   17 17)
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "sdiv")
+       (eq_attr "cpu" "ppc7450"))
+  21 21)
+
+(define_function_unit "fpu" 1 0
+  (and (eq_attr "type" "sdiv")
        (eq_attr "cpu" "mpccore"))
   10 10)
 
@@ -471,11 +551,16 @@
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "ddiv")
-       (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620"))
+       (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620,ppc7400"))
   31 31)
 
 (define_function_unit "fpu" 1 0
   (and (eq_attr "type" "ddiv")
+       (eq_attr "cpu" "ppc7450"))
+  35 35)
+
+(define_function_unit "fpu" 1 0
+  (and (eq_attr "type" "ddiv")
        (eq_attr "cpu" "ppc603"))
   33 33)
 

gcc/doc/invoke.texi

@@ -6587,9 +6587,9 @@ instruction scheduling parameters for machine type @var{cpu_type}.
 Supported values for @var{cpu_type} are @samp{rios}, @samp{rios1},
 @samp{rsc}, @samp{rios2}, @samp{rs64a}, @samp{601}, @samp{602},
 @samp{603}, @samp{603e}, @samp{604}, @samp{604e}, @samp{620},
-@samp{630}, @samp{740}, @samp{750}, @samp{power}, @samp{power2},
-@samp{powerpc}, @samp{403}, @samp{505}, @samp{801}, @samp{821},
-@samp{823}, and @samp{860} and @samp{common}.
+@samp{630}, @samp{740}, @samp{7400}, @samp{7450}, @samp{750},
+@samp{power}, @samp{power2}, @samp{powerpc}, @samp{403}, @samp{505},
+@samp{801}, @samp{821}, @samp{823}, and @samp{860} and @samp{common}.
 
 @option{-mcpu=common} selects a completely generic processor.  Code
 generated under this option will run on any POWER or PowerPC processor.
@@ -6630,6 +6630,8 @@ The @option{-mcpu} options automatically enable or disable other
 @itemx 620
 @itemx 630
 @itemx 740
+@itemx 7400
+@itemx 7450
 @itemx 750
 @itemx 505
 @option{-mno-power}, @option{-mpowerpc}, @option{-mnew-mnemonics}