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riscv-gcc-1
Commit ed69105c by Richard Henderson Committed by Richard Henderson
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constraints.md (Ym): New constraint. 

        * config/i386/constraints.md (Ym): New constraint.
        * config/i386/i386.md (movsi_1): Change Y2 to Yi constraints.
        (movdi_1_rex64): Split sse and xmm general register moves from
        memory move alternatives.  Use conditional register constraints.
        (movsf_1, movdf_integer): Likewise.
        (zero_extendsidi2_32, zero_extendsidi2_rex64): Likewise.
        (movdf_integer_rex64): New.
        (pushsf_rex64): Fix output constraints.
        * config/i386/sse.md (sse2_loadld): Split rm alternative, use Yi.
        (sse2_stored): Likewise.
        (sse2_storeq_rex64): New.
        * config/i386/i386.c (x86_inter_unit_moves): Enable for not
        amd and not generic.
        (ix86_secondary_memory_needed): Don't bypass TARGET_INTER_UNIT_MOVES
        for optimize_size.  Remove SF/DFmode hack.

From-SVN: r121767
parent 8413669b
Showing with 40 additions and 20 deletions
gcc/ChangeLog
2007-02-09 Richard Henderson <rth@redhat.com>
* config/i386/constraints.md (Ym): New constraint.
* config/i386/i386.md (movsi_1): Change Y2 to Yi constraints.
(movdi_1_rex64): Split sse and xmm general register moves from
memory move alternatives. Use conditional register constraints.
(movsf_1, movdf_integer): Likewise.
(zero_extendsidi2_32, zero_extendsidi2_rex64): Likewise.
(movdf_integer_rex64): New.
(pushsf_rex64): Fix output constraints.
* config/i386/sse.md (sse2_loadld): Split rm alternative, use Yi.
(sse2_stored): Likewise.
(sse2_storeq_rex64): New.
* config/i386/i386.c (x86_inter_unit_moves): Enable for not
amd and not generic.
(ix86_secondary_memory_needed): Don't bypass TARGET_INTER_UNIT_MOVES
for optimize_size. Remove SF/DFmode hack.
2007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10.
......
gcc/config/i386/constraints.md
......@@ -86,6 +86,7 @@
;; We use the Y prefix to denote any number of conditional register sets:
;; 2 SSE2 enabled
;; i SSE2 inter-unit moves enabled
;; m MMX inter-unit moves enabled
(define_register_constraint "Y2" "TARGET_SSE2 ? SSE_REGS : NO_REGS"
"@internal Any SSE register, when SSE2 is enabled.")
......@@ -94,6 +95,10 @@
"TARGET_SSE2 && TARGET_INTER_UNIT_MOVES ? SSE_REGS : NO_REGS"
"@internal Any SSE register, when SSE2 and inter-unit moves are enabled.")
(define_register_constraint "Ym"
"TARGET_MMX && TARGET_INTER_UNIT_MOVES ? MMX_REGS : NO_REGS"
"@internal Any MMX register, when inter-unit moves are enabled.")
;; Integer constant constraints.
(define_constraint "I"
"Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
......
gcc/config/i386/i386.c
......@@ -1161,9 +1161,7 @@ const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
const int x86_use_ffreep = m_ATHLON_K8_AMDFAM10;
const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC);
/* ??? Allowing interunit moves makes it all too easy for the compiler to put
integer data in xmm registers. Which results in pretty abysmal code. */
const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;
const int x86_inter_unit_moves = ~(m_ATHLON_K8_AMDFAM10 | m_GENERIC);
const int x86_ext_80387_constants = m_K6_GEODE | m_ATHLON_K8 | m_PENT4
| m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
......@@ -18301,18 +18299,12 @@ ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
/* If the target says that inter-unit moves are more expensive
than moving through memory, then don't generate them. */
if (!TARGET_INTER_UNIT_MOVES && !optimize_size)
if (!TARGET_INTER_UNIT_MOVES)
return true;
/* Between SSE and general, we have moves no larger than word size. */
if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
return true;
/* ??? For the cost of one register reformat penalty, we could use
the same instructions to move SFmode and DFmode data, but the
relevant move patterns don't support those alternatives. */
if (mode == SFmode || mode == DFmode)
return true;
}
return false;
......
gcc/config/i386/sse.md
......@@ -3961,26 +3961,25 @@
"operands[2] = CONST0_RTX (V4SImode);")
(define_insn "sse2_loadld"
[(set (match_operand:V4SI 0 "register_operand" "=Y2,x,x")
[(set (match_operand:V4SI 0 "register_operand" "=Y2,Yi,x,x")
(vec_merge:V4SI
(vec_duplicate:V4SI
(match_operand:SI 2 "nonimmediate_operand" "mr ,m,x"))
(match_operand:V4SI 1 "reg_or_0_operand" " C ,C,0")
(match_operand:SI 2 "nonimmediate_operand" "m ,r ,m,x"))
(match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,C,0")
(const_int 1)))]
"TARGET_SSE"
"@
movd\t{%2, %0|%0, %2}
movd\t{%2, %0|%0, %2}
movss\t{%2, %0|%0, %2}
movss\t{%2, %0|%0, %2}"
[(set_attr "type" "ssemov")
(set_attr "mode" "TI,V4SF,SF")])
(set_attr "mode" "TI,TI,V4SF,SF")])
;; ??? The hardware supports more, but TARGET_INTER_UNIT_MOVES must
;; be taken into account, and movdi isn't fully populated even without.
(define_insn_and_split "sse2_stored"
[(set (match_operand:SI 0 "nonimmediate_operand" "=mx")
[(set (match_operand:SI 0 "nonimmediate_operand" "=mx,r")
(vec_select:SI
(match_operand:V4SI 1 "register_operand" "x")
(match_operand:V4SI 1 "register_operand" "x,Yi")
(parallel [(const_int 0)])))]
"TARGET_SSE"
"#"
......@@ -3998,8 +3997,14 @@
"TARGET_SSE"
"")
;; ??? The hardware supports more, but TARGET_INTER_UNIT_MOVES must
;; be taken into account, and movdi isn't fully populated even without.
(define_insn "*sse2_storeq_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=mx,r")
(vec_select:DI
(match_operand:V2DI 1 "register_operand" "x,Yi")
(parallel [(const_int 0)])))]
"TARGET_64BIT && TARGET_SSE"
"#")
(define_insn "*sse2_storeq"
[(set (match_operand:DI 0 "nonimmediate_operand" "=mx")
(vec_select:DI
......
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