RISC-V: Set SLOW_BYTE_ACCESS=1

When implementing the RISC-V port, I took the name of this macro at
face value.  It appears we were mistaken in what this means, here's a
quote from the SPARC port that better describes what SLOW_BYTE_ACCESS
does

    /* Nonzero if access to memory by bytes is slow and undesirable.
       For RISC chips, it means that access to memory by bytes is no
       better than access by words when possible, so grab a whole word
       and maybe make use of that.  */

I've added the comment to our port as well.

See https://gcc.gnu.org/ml/gcc/2017-08/msg00202.html for more
discussion.  Thanks to Michael Clark and Andrew Pinski for the help!

gcc/ChangeLog

2017-11-04  Andrew Waterman  <andrew@sifive.com>

        * config/riscv/riscv.h (SLOW_BYTE_ACCESS): Change to 1.

From-SVN: r254416

gcc/ChangeLog

+2017-11-04  Andrew Waterman  <andrew@sifive.com>
+
+	* config/riscv/riscv.h (SLOW_BYTE_ACCESS): Change to 1.
+
 2017-11-04  Daniel Santos  <daniel.santos@pobox.com>
 
 	config/i386/i386.c (choose_basereg): Use optional scratch

gcc/config/riscv/riscv.h

@@ -615,7 +615,12 @@ typedef struct {
 #define MOVE_MAX UNITS_PER_WORD
 #define MAX_MOVE_MAX 8
 
-#define SLOW_BYTE_ACCESS 0
+/* The SPARC port says:
+   Nonzero if access to memory by bytes is slow and undesirable.
+   For RISC chips, it means that access to memory by bytes is no
+   better than access by words when possible, so grab a whole word
+   and maybe make use of that.  */
+#define SLOW_BYTE_ACCESS 1
 
 #define SHIFT_COUNT_TRUNCATED 1