re PR target/71677 (PowerPC ISA 3.0 DImode load/store needs a fix)

2016-06-30  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71677
	* config/rs6000/constraints.md (wY constraint): New constraint to
	match the requirements for the LXSD and STXSD instructions.
	* config/rs6000/predicates.md (offsettable_mem_14bit_operand): New
	predicate to match the requirements for the LXSD and STXSD
	instructions.
	* config/rs6000/rs6000.md (mov<mode>_hardfloat32, FMOVE64 case):
	Use constaint wY for LXSD/STXSD instructions instead of 'o' or 'Y'
	to make sure that the bottom 2 bits of offset are 0, the address
	form is offsettable, and no updating is done in the address mode.
	(mov<mode>_hardfloat64, FMOVE64 case): Likewise.
	(movdi_internal32): Likewise
	(movdi_internal64): Likewise.

From-SVN: r237898

gcc/ChangeLog

+2016-06-30  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/71677
+	* config/rs6000/constraints.md (wY constraint): New constraint to
+	match the requirements for the LXSD and STXSD instructions.
+	* config/rs6000/predicates.md (offsettable_mem_14bit_operand): New
+	predicate to match the requirements for the LXSD and STXSD
+	instructions.
+	* config/rs6000/rs6000.md (mov<mode>_hardfloat32, FMOVE64 case):
+	Use constaint wY for LXSD/STXSD instructions instead of 'o' or 'Y'
+	to make sure that the bottom 2 bits of offset are 0, the address
+	form is offsettable, and no updating is done in the address mode.
+	(mov<mode>_hardfloat64, FMOVE64 case): Likewise.
+	(movdi_internal32): Likewise
+	(movdi_internal64): Likewise.
+
 2016-06-30  Jakub Jelinek  <jakub@redhat.com>
 
 	PR tree-optimization/71707

gcc/config/rs6000/constraints.md

@@ -185,6 +185,11 @@
   "Vector constant that can be loaded with XXSPLTIB & sign extension."
   (match_test "xxspltib_constant_split (op, mode)"))
 
+;; ISA 3.0 D-form instruction that has the bottom 2 bits 0 (LXSD or STXSD).
+(define_memory_constraint "wY"
+  "Offsettable memory operand, with bottom 2 bits 0"
+  (match_operand 0 "offsettable_mem_14bit_operand"))
+
 ;; Altivec style load/store that ignores the bottom bits of the address
 (define_memory_constraint "wZ"
   "Indexed or indirect memory operand, ignoring the bottom 4 bits"

gcc/config/rs6000/predicates.md

@@ -734,6 +734,15 @@
   (and (match_operand 0 "memory_operand")
        (match_test "offsettable_nonstrict_memref_p (op)")))
 
+;; Return 1 if the operand is an offsettable memory operand for ISA 3.0
+;; scalar LXSD/STXSD that must have the bottom 2 bits 0 and no update
+;; form
+(define_predicate "offsettable_mem_14bit_operand"
+  (and (match_operand 0 "memory_operand")
+       (match_test "offsettable_nonstrict_memref_p (op)")
+       (match_test "mem_operand_gpr (op, mode)")
+       (not (match_test "update_address_mem  (op, mode)"))))
+
 ;; Return 1 if the operand is suitable for load/store quad memory.
 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
 (define_predicate "quad_memory_operand"

gcc/config/rs6000/rs6000.md

@@ -6775,8 +6775,8 @@
 ;; except for 0.0 which can be created on VSX with an xor instruction.
 
 (define_insn "*mov<mode>_hardfloat32"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_p9>,o,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
-	(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,o,<f64_p9>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_p9>,wY,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
+	(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,wY,<f64_p9>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
@@ -6814,8 +6814,8 @@
 ; ld/std require word-aligned displacements -> 'Y' constraint.
 ; List Y->r and r->Y before r->r for reload.
 (define_insn "*mov<mode>_hardfloat64"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,o,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,<f64_dm>")
-	(match_operand:FMOVE64 1 "input_operand" "d,m,d,o,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,<f64_dm>")
+	(match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))]
   "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7856,13 +7856,13 @@
 (define_insn "*movdi_internal32"
   [(set (match_operand:DI 0 "rs6000_nonimmediate_operand"
          "=Y,        r,         r,         ?m,        ?*d,        ?*d,
-          r,         ?Y,        ?Z,        ?*wb,      ?*wv,       ?wi,
+          r,         ?wY,       ?Z,        ?*wb,      ?*wv,       ?wi,
           ?wo,       ?wo,       ?wv,       ?wi,       ?wi,        ?wv,
           ?wv")
 
 	(match_operand:DI 1 "input_operand"
           "r,        Y,         r,         d,         m,          d,
-           IJKnGHF,  wb,        wv,        Y,         Z,          wi,
+           IJKnGHF,  wb,        wv,        wY,        Z,          wi,
            Oj,       wM,        OjwM,      Oj,        wM,         wS,
            wB"))]
 
@@ -7932,14 +7932,14 @@
 (define_insn "*movdi_internal64"
   [(set (match_operand:DI 0 "nonimmediate_operand"
                "=Y,        r,         r,         r,         r,          r,
-                ?m,        ?*d,       ?*d,       ?Y,        ?Z,         ?*wb,
+                ?m,        ?*d,       ?*d,       ?wY,       ?Z,         ?*wb,
                 ?*wv,      ?wi,       ?wo,       ?wo,       ?wv,        ?wi,
                 ?wi,       ?wv,       ?wv,       r,         *h,         *h,
                 ?*r,       ?*wg,      ?*r,       ?*wj")
 
 	(match_operand:DI 1 "input_operand"
                 "r,        Y,         r,         I,         L,          nF,
-                 d,        m,         d,         wb,        wv,         Y,
+                 d,        m,         d,         wb,        wv,         wY,
                  Z,        wi,        Oj,        wM,        OjwM,       Oj,
                  wM,       wS,        wB,        *h,        r,          0,
                  wg,       r,         wj,        r"))]