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riscv-gcc-1
Commit eb8da868 by Richard Henderson
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alpha.c (reg_or_6bit_operand): Remove CONSTANT_P_RTX handling. 

        * alpha.c (reg_or_6bit_operand): Remove CONSTANT_P_RTX handling.
        (reg_or_8bit_operand, cint8_operand, add_operand): Likewise.
        (sext_add_operand, and_operand, or_operand): Likewise.
        (reg_or_cint_operand, some_operand, input_operand): Likewise.
        * alpha.h (PREDICATE_CODES): Likewise.

From-SVN: r24438
parent 8f8e7de3
Showing with 12 additions and 25 deletions
gcc/config/alpha/alpha.c
...@@ -348,7 +348,6 @@ reg_or_6bit_operand (op, mode) ...@@ -348,7 +348,6 @@ reg_or_6bit_operand (op, mode)
{ {
return ((GET_CODE (op) == CONST_INT return ((GET_CODE (op) == CONST_INT
&& (unsigned HOST_WIDE_INT) INTVAL (op) < 64) && (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
|| GET_CODE (op) == CONSTANT_P_RTX
|| register_operand (op, mode)); || register_operand (op, mode));
} }
...@@ -362,7 +361,6 @@ reg_or_8bit_operand (op, mode) ...@@ -362,7 +361,6 @@ reg_or_8bit_operand (op, mode)
{ {
return ((GET_CODE (op) == CONST_INT return ((GET_CODE (op) == CONST_INT
&& (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100) && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
|| GET_CODE (op) == CONSTANT_P_RTX
|| register_operand (op, mode)); || register_operand (op, mode));
} }
...@@ -374,8 +372,7 @@ cint8_operand (op, mode) ...@@ -374,8 +372,7 @@ cint8_operand (op, mode)
enum machine_mode mode ATTRIBUTE_UNUSED; enum machine_mode mode ATTRIBUTE_UNUSED;
{ {
return ((GET_CODE (op) == CONST_INT return ((GET_CODE (op) == CONST_INT
&& (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100) && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100));
|| GET_CODE (op) == CONSTANT_P_RTX);
} }
/* Return 1 if the operand is a valid second operand to an add insn. */ /* Return 1 if the operand is a valid second operand to an add insn. */
...@@ -389,8 +386,6 @@ add_operand (op, mode) ...@@ -389,8 +386,6 @@ add_operand (op, mode)
/* Constraints I, J, O and P are covered by K. */ /* Constraints I, J, O and P are covered by K. */
return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K') return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
|| CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
else if (GET_CODE (op) == CONSTANT_P_RTX)
return 1;
return register_operand (op, mode); return register_operand (op, mode);
} }
...@@ -406,8 +401,6 @@ sext_add_operand (op, mode) ...@@ -406,8 +401,6 @@ sext_add_operand (op, mode)
if (GET_CODE (op) == CONST_INT) if (GET_CODE (op) == CONST_INT)
return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
|| CONST_OK_FOR_LETTER_P (INTVAL (op), 'O')); || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'));
else if (GET_CODE (op) == CONSTANT_P_RTX)
return 1;
return register_operand (op, mode); return register_operand (op, mode);
} }
...@@ -438,8 +431,6 @@ and_operand (op, mode) ...@@ -438,8 +431,6 @@ and_operand (op, mode)
return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
|| (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
|| zap_mask (INTVAL (op))); || zap_mask (INTVAL (op)));
else if (GET_CODE (op) == CONSTANT_P_RTX)
return 1;
return register_operand (op, mode); return register_operand (op, mode);
} }
...@@ -454,8 +445,6 @@ or_operand (op, mode) ...@@ -454,8 +445,6 @@ or_operand (op, mode)
if (GET_CODE (op) == CONST_INT) if (GET_CODE (op) == CONST_INT)
return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
|| (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100); || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
else if (GET_CODE (op) == CONSTANT_P_RTX)
return 1;
return register_operand (op, mode); return register_operand (op, mode);
} }
...@@ -555,7 +544,6 @@ reg_or_cint_operand (op, mode) ...@@ -555,7 +544,6 @@ reg_or_cint_operand (op, mode)
enum machine_mode mode; enum machine_mode mode;
{ {
return (GET_CODE (op) == CONST_INT return (GET_CODE (op) == CONST_INT
|| GET_CODE (op) == CONSTANT_P_RTX
|| register_operand (op, mode)); || register_operand (op, mode));
} }
...@@ -573,7 +561,7 @@ some_operand (op, mode) ...@@ -573,7 +561,7 @@ some_operand (op, mode)
switch (GET_CODE (op)) switch (GET_CODE (op))
{ {
case REG: case MEM: case CONST_DOUBLE: case CONST_INT: case LABEL_REF: case REG: case MEM: case CONST_DOUBLE: case CONST_INT: case LABEL_REF:
case SYMBOL_REF: case CONST: case CONSTANT_P_RTX: case SYMBOL_REF: case CONST:
return 1; return 1;
case SUBREG: case SUBREG:
...@@ -622,7 +610,6 @@ input_operand (op, mode) ...@@ -622,7 +610,6 @@ input_operand (op, mode)
return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
case CONST_INT: case CONST_INT:
case CONSTANT_P_RTX:
return mode == QImode || mode == HImode || add_operand (op, mode); return mode == QImode || mode == HImode || add_operand (op, mode);
default: default:
......
gcc/config/alpha/alpha.h
...@@ -2265,15 +2265,15 @@ do { \ ...@@ -2265,15 +2265,15 @@ do { \
#define PREDICATE_CODES \ #define PREDICATE_CODES \
{"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
{"cint8_operand", {CONST_INT, CONSTANT_P_RTX}}, \ {"cint8_operand", {CONST_INT}}, \
{"reg_or_cint_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
{"add_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ {"add_operand", {SUBREG, REG, CONST_INT}}, \
{"sext_add_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
{"const48_operand", {CONST_INT}}, \ {"const48_operand", {CONST_INT}}, \
{"and_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ {"and_operand", {SUBREG, REG, CONST_INT}}, \
{"or_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ {"or_operand", {SUBREG, REG, CONST_INT}}, \
{"mode_mask_operand", {CONST_INT}}, \ {"mode_mask_operand", {CONST_INT}}, \
{"mul8_operand", {CONST_INT}}, \ {"mul8_operand", {CONST_INT}}, \
{"mode_width_operand", {CONST_INT}}, \ {"mode_width_operand", {CONST_INT}}, \
...@@ -2286,9 +2286,9 @@ do { \ ...@@ -2286,9 +2286,9 @@ do { \
{"current_file_function_operand", {SYMBOL_REF}}, \ {"current_file_function_operand", {SYMBOL_REF}}, \
{"call_operand", {REG, SYMBOL_REF}}, \ {"call_operand", {REG, SYMBOL_REF}}, \
{"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
SYMBOL_REF, CONST, LABEL_REF, CONSTANT_P_RTX}}, \ SYMBOL_REF, CONST, LABEL_REF}}, \
{"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
SYMBOL_REF, CONST, LABEL_REF, CONSTANT_P_RTX}}, \ SYMBOL_REF, CONST, LABEL_REF}}, \
{"aligned_memory_operand", {MEM}}, \ {"aligned_memory_operand", {MEM}}, \
{"unaligned_memory_operand", {MEM}}, \ {"unaligned_memory_operand", {MEM}}, \
{"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \ {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
......
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