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riscv-gcc-1
Commit eabd294f by Richard Henderson Committed by Richard Henderson
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* config/i386/i386.c (ix86_prepare_fp_compare_args): Fix is_sse test. 

From-SVN: r94085
parent 5ccbd309
Showing with 5 additions and 1 deletions
gcc/ChangeLog
2005-01-22 Richard Henderson <rth@redhat.com> 2005-01-22 Richard Henderson <rth@redhat.com>
* config/i386/i386.c (ix86_prepare_fp_compare_args): Fix is_sse test.
2005-01-22 Richard Henderson <rth@redhat.com>
* genopinit.c (optabs): Use smin/smax for floating point too. * genopinit.c (optabs): Use smin/smax for floating point too.
* doc/md.texi: Update to match. Clarify that floating point * doc/md.texi: Update to match. Clarify that floating point
results are undefined for +0/-0 and NaN. results are undefined for +0/-0 and NaN.
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gcc/config/i386/i386.c
...@@ -8331,7 +8331,7 @@ ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1) ...@@ -8331,7 +8331,7 @@ ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code); enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
rtx op0 = *pop0, op1 = *pop1; rtx op0 = *pop0, op1 = *pop1;
enum machine_mode op_mode = GET_MODE (op0); enum machine_mode op_mode = GET_MODE (op0);
int is_sse = SSE_REG_P (op0) || SSE_REG_P (op1); int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
/* All of the unordered compare instructions only work on registers. /* All of the unordered compare instructions only work on registers.
The same is true of the fcomi compare instructions. The same is The same is true of the fcomi compare instructions. The same is
......
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