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Commit eaa17c21 by Uros Bizjak Committed by Uros Bizjak
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i386.md (FPSR_REG): Remove. 

	* config/i386/i386.md (FPSR_REG): Remove.
	(x86_fnstcw_1): Use (const_int 0) instead of FPCR_REG.
	(x86_fldcw_1): Remove insn pattern.
	(fnstenv): Do not clobber FPCR_REG.
	(fldenv): Ditto.
	* config/i386/i386.h (FIXED_REGISTERS) Remove fpsr register.
	(CALL_USED_REGISTERS): Ditto.
	(REG_ALLOC_ORDER): Ditto.
	(REG_CLASS_CONTENTS): Ditto.
	(HI_REGISTER_NAMES): Ditto.
	(ADDITIONAL_REGISTER_NAMES): Use defines instead
	of numerical constants.
	* config/i386/i386.c (regclass_map): Remove fpsr register.
	(dbx_register_map): Ditto.
	(dbx64_register_map): Ditto.
	(svr4_dbx_register_map): Ditto.
	(print_reg): Do not handle FPCR_REG.

testsuite/ChangeLog:

	* gcc.dg/rtl/x86_64/dfinit.c: Update scan-rtl-dump string.
	* gcc.dg/rtl/x86_64/times-two.c.before-df.c: Ditto.
	* gcc.target/i386/pr79804.c (foo): Use register "19", not "20".

From-SVN: r264676
parent 24676f12
Showing with 162 additions and 153 deletions
gcc/ChangeLog
2018-09-27 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (FPSR_REG): Remove.
(x86_fnstcw_1): Use (const_int 0) instead of FPCR_REG.
(x86_fldcw_1): Remove insn pattern.
(fnstenv): Do not clobber FPCR_REG.
(fldenv): Ditto.
* config/i386/i386.h (FIXED_REGISTERS) Remove fpsr register.
(CALL_USED_REGISTERS): Ditto.
(REG_ALLOC_ORDER): Ditto.
(REG_CLASS_CONTENTS): Ditto.
(HI_REGISTER_NAMES): Ditto.
(ADDITIONAL_REGISTER_NAMES): Use defines instead
of numerical constants.
* config/i386/i386.c (regclass_map): Remove fpsr register.
(dbx_register_map): Ditto.
(dbx64_register_map): Ditto.
(svr4_dbx_register_map): Ditto.
(print_reg): Do not handle FPCR_REG.
2018-09-27 Segher Boessenkool <segher@kernel.crashing.org>
PR target/87149
......
gcc/config/i386/i386.c
......@@ -241,10 +241,8 @@ enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
/* FP registers */
FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
/* arg pointer */
NON_Q_REGS,
/* flags, fpsr, fpcr, frame */
NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
/* arg pointer, flags, fpsr, frame */
NON_Q_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
/* SSE registers */
SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS,
SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
......@@ -273,7 +271,7 @@ int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
{
0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
-1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
-1, -1, -1, -1, /* arg, flags, fpsr, frame */
21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
-1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
......@@ -289,7 +287,7 @@ int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
{
0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
-1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
-1, -1, -1, -1, /* arg, flags, fpsr, frame */
17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
8,9,10,11,12,13,14,15, /* extended integer registers */
......@@ -357,7 +355,7 @@ int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
{
0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
-1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
-1, 9, -1, -1, /* arg, flags, fpsr, frame */
21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
-1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
......@@ -17372,8 +17370,7 @@ print_reg (rtx x, int code, FILE *file)
if (regno == ARG_POINTER_REGNUM
|| regno == FRAME_POINTER_REGNUM
|| regno == FPSR_REG
|| regno == FPCR_REG)
|| regno == FPSR_REG)
{
output_operand_lossage
("invalid use of register '%s'", reg_names[regno]);
gcc/config/i386/i386.md
......@@ -359,65 +359,64 @@
(ARGP_REG 16)
(FLAGS_REG 17)
(FPSR_REG 18)
(FPCR_REG 19)
(FRAME_REG 20)
(XMM0_REG 21)
(XMM1_REG 22)
(XMM2_REG 23)
(XMM3_REG 24)
(XMM4_REG 25)
(XMM5_REG 26)
(XMM6_REG 27)
(XMM7_REG 28)
(MM0_REG 29)
(MM1_REG 30)
(MM2_REG 31)
(MM3_REG 32)
(MM4_REG 33)
(MM5_REG 34)
(MM6_REG 35)
(MM7_REG 36)
(R8_REG 37)
(R9_REG 38)
(R10_REG 39)
(R11_REG 40)
(R12_REG 41)
(R13_REG 42)
(R14_REG 43)
(R15_REG 44)
(XMM8_REG 45)
(XMM9_REG 46)
(XMM10_REG 47)
(XMM11_REG 48)
(XMM12_REG 49)
(XMM13_REG 50)
(XMM14_REG 51)
(XMM15_REG 52)
(XMM16_REG 53)
(XMM17_REG 54)
(XMM18_REG 55)
(XMM19_REG 56)
(XMM20_REG 57)
(XMM21_REG 58)
(XMM22_REG 59)
(XMM23_REG 60)
(XMM24_REG 61)
(XMM25_REG 62)
(XMM26_REG 63)
(XMM27_REG 64)
(XMM28_REG 65)
(XMM29_REG 66)
(XMM30_REG 67)
(XMM31_REG 68)
(MASK0_REG 69)
(MASK1_REG 70)
(MASK2_REG 71)
(MASK3_REG 72)
(MASK4_REG 73)
(MASK5_REG 74)
(MASK6_REG 75)
(MASK7_REG 76)
(FIRST_PSEUDO_REG 77)
(FRAME_REG 19)
(XMM0_REG 20)
(XMM1_REG 21)
(XMM2_REG 22)
(XMM3_REG 23)
(XMM4_REG 24)
(XMM5_REG 25)
(XMM6_REG 26)
(XMM7_REG 27)
(MM0_REG 28)
(MM1_REG 29)
(MM2_REG 30)
(MM3_REG 31)
(MM4_REG 32)
(MM5_REG 33)
(MM6_REG 34)
(MM7_REG 35)
(R8_REG 36)
(R9_REG 37)
(R10_REG 38)
(R11_REG 39)
(R12_REG 40)
(R13_REG 41)
(R14_REG 42)
(R15_REG 43)
(XMM8_REG 44)
(XMM9_REG 45)
(XMM10_REG 46)
(XMM11_REG 47)
(XMM12_REG 48)
(XMM13_REG 49)
(XMM14_REG 50)
(XMM15_REG 51)
(XMM16_REG 52)
(XMM17_REG 53)
(XMM18_REG 54)
(XMM19_REG 55)
(XMM20_REG 56)
(XMM21_REG 57)
(XMM22_REG 58)
(XMM23_REG 59)
(XMM24_REG 60)
(XMM25_REG 61)
(XMM26_REG 62)
(XMM27_REG 63)
(XMM28_REG 64)
(XMM29_REG 65)
(XMM30_REG 66)
(XMM31_REG 67)
(MASK0_REG 68)
(MASK1_REG 69)
(MASK2_REG 70)
(MASK3_REG 71)
(MASK4_REG 72)
(MASK5_REG 73)
(MASK6_REG 74)
(MASK7_REG 75)
(FIRST_PSEUDO_REG 76)
])
;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
......@@ -5043,7 +5042,7 @@
(define_insn "x86_fnstcw_1"
[(set (match_operand:HI 0 "memory_operand" "=m")
(unspec:HI [(reg:HI FPCR_REG)] UNSPEC_FSTCW))]
(unspec:HI [(const_int 0)] UNSPEC_FSTCW))]
"TARGET_80387"
"fnstcw\t%0"
[(set (attr "length")
......@@ -5051,19 +5050,6 @@
(set_attr "mode" "HI")
(set_attr "unit" "i387")
(set_attr "bdver1_decode" "vector")])
(define_insn "x86_fldcw_1"
[(set (reg:HI FPCR_REG)
(unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
"TARGET_80387"
"fldcw\t%0"
[(set (attr "length")
(symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "HI")
(set_attr "unit" "i387")
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "vector")
(set_attr "bdver1_decode" "vector")])
;; Conversion between fixed point and floating point.
......@@ -19603,7 +19589,6 @@
(define_insn "fnstenv"
[(set (match_operand:BLK 0 "memory_operand" "=m")
(unspec_volatile:BLK [(const_int 0)] UNSPECV_FNSTENV))
(clobber (reg:HI FPCR_REG))
(clobber (reg:XF ST0_REG))
(clobber (reg:XF ST1_REG))
(clobber (reg:XF ST2_REG))
......@@ -19623,7 +19608,6 @@
[(unspec_volatile [(match_operand:BLK 0 "memory_operand" "m")]
UNSPECV_FLDENV)
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:HI FPCR_REG))
(clobber (reg:XF ST0_REG))
(clobber (reg:XF ST1_REG))
(clobber (reg:XF ST2_REG))
......
gcc/testsuite/ChangeLog
2018-09-27 Uros Bizjak <ubizjak@gmail.com>
* gcc.dg/rtl/x86_64/dfinit.c: Update scan-rtl-dump string.
* gcc.dg/rtl/x86_64/times-two.c.before-df.c: Ditto.
* gcc.target/i386/pr79804.c (foo): Use register "19", not "20".
2018-09-27 Martin Liska <mliska@suse.cz>
* g++.dg/pr60518.C: Add -Wno-missing-profile.
......
gcc/testsuite/gcc.dg/rtl/x86_64/dfinit.c
......@@ -112,5 +112,5 @@ int __RTL (startwith ("no-opt dfinit")) test_1 (int i, int j, int k)
frontend, the exit block use of reg 0 (ax) wasn't picked up
on, due to not setting up crtl->return_rtx based on
DECL_RESULT (fndecl). */
/* { dg-final { scan-rtl-dump ";; exit block uses.*0 .ax. 6 .bp. 7 .sp. 20 .frame." "dfinit" } } */
/* { dg-final { scan-rtl-dump ";; exit block uses.*0 .ax. 6 .bp. 7 .sp. 19 .frame." "dfinit" } } */
/* { dg-final { scan-rtl-dump ";; regs ever live.*0 .ax. 1 .dx. 4 .si. 5 .di. 17 .flags." "dfinit" } } */
gcc/testsuite/gcc.dg/rtl/x86_64/times-two.c.before-df.c
......@@ -49,6 +49,6 @@ int __RTL (startwith ("rtl-dfinit")) times_two (int i)
on, due to not setting up crtl->return_rtx based on
DECL_RESULT (fndecl). */
/* { dg-final { scan-rtl-dump ";; exit block uses.*0 .ax. 6 .bp. 7 .sp. 20 .frame." "dfinit" } } */
/* { dg-final { scan-rtl-dump ";; exit block uses.*0 .ax. 6 .bp. 7 .sp. 19 .frame." "dfinit" } } */
/* { dg-final { scan-rtl-dump ";; regs ever live.*0 .ax. 5 .di. 17 .flags." "dfinit" } } */
gcc/testsuite/gcc.target/i386/pr79804.c
......@@ -4,7 +4,7 @@
void foo (void)
{
register int r20 asm ("20");
register int r19 asm ("19");
asm volatile ("# %0" : "=r"(r20)); /* { dg-error "invalid use of register" } */
asm volatile ("# %0" : "=r"(r19)); /* { dg-error "invalid use of register" } */
} /* { dg-error "cannot be used in asm here" } */
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