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riscv-gcc-1
Commit ea112fc4 by David Edelsohn Committed by David Edelsohn
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rs6000.md (abssi2_nopower): Convert to define_insn_and_split. 

        * rs6000.md (abssi2_nopower): Convert to define_insn_and_split.
        (nabs_nopower): Same.
        (floatdisf2): New pattern.
        (absdi2): Convert to define_insn_and_split.
        (nabsdi2): Same.
        (trunctfsf2): Same.
        (floatditf2): Same.
        (floatsitf2): Same.
        (fix_trunctfdi2): Same.
        (fix_trunctfsi2): Same.

From-SVN: r52999
parent dda78254
Showing with 80 additions and 71 deletions
gcc/ChangeLog
2002-05-01 David Edelsohn <edelsohn@gnu.org>
* rs6000.md (abssi2_nopower): Convert to define_insn_and_split.
(nabs_nopower): Same.
(floatdisf2): New pattern.
(absdi2): Convert to define_insn_and_split.
(nabsdi2): Same.
(trunctfsf2): Same.
(floatditf2): Same.
(floatsitf2): Same.
(fix_trunctfdi2): Same.
(fix_trunctfsi2): Same.
2002-05-01 Joseph S. Myers <jsm28@cam.ac.uk> 2002-05-01 Joseph S. Myers <jsm28@cam.ac.uk>
* doc/install.texi: Update Texinfo version requirement * doc/install.texi: Update Texinfo version requirement
......
gcc/config/rs6000/rs6000.md
...@@ -2114,30 +2114,19 @@ ...@@ -2114,30 +2114,19 @@
} }
}") }")
(define_insn "abssi2_power" (define_insn "*abssi2_power"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
"TARGET_POWER" "TARGET_POWER"
"abs %0,%1") "abs %0,%1")
(define_insn "abssi2_nopower" (define_insn_and_split "abssi2_nopower"
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
(clobber (match_scratch:SI 2 "=&r,&r"))] (clobber (match_scratch:SI 2 "=&r,&r"))]
"! TARGET_POWER" "! TARGET_POWER"
"* "#"
{ "&& reload_completed"
return (TARGET_POWERPC)
? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
: \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
}"
[(set_attr "length" "12")])
(define_split
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
(clobber (match_scratch:SI 2 ""))]
"! TARGET_POWER && reload_completed"
[(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
...@@ -2149,24 +2138,13 @@ ...@@ -2149,24 +2138,13 @@
"TARGET_POWER" "TARGET_POWER"
"nabs %0,%1") "nabs %0,%1")
(define_insn "*nabs_no_power" (define_insn_and_split "*nabs_nopower"
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
(clobber (match_scratch:SI 2 "=&r,&r"))] (clobber (match_scratch:SI 2 "=&r,&r"))]
"! TARGET_POWER" "! TARGET_POWER"
"* "#"
{ "&& reload_completed"
return (TARGET_POWERPC)
? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
: \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
}"
[(set_attr "length" "12")])
(define_split
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))))
(clobber (match_scratch:SI 2 ""))]
"! TARGET_POWER && reload_completed"
[(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
...@@ -5462,6 +5440,20 @@ ...@@ -5462,6 +5440,20 @@
"TARGET_POWERPC64 && TARGET_HARD_FLOAT" "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"fctidz %0,%1" "fctidz %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
;; This only is safe if rounding mode set appropriately.
(define_insn_and_split "floatdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "f")))
(clobber (match_scratch:DF 2 "=f"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
"#"
"&& reload_completed"
[(set (match_dup 2)
(float:DF (match_dup 1)))
(set (match_dup 0)
(float_truncate:SF (match_dup 2)))]
"")
;; Define the DImode operations that can be done in a small number ;; Define the DImode operations that can be done in a small number
;; of instructions. The & constraints are to prevent the register ;; of instructions. The & constraints are to prevent the register
...@@ -6070,37 +6062,25 @@ ...@@ -6070,37 +6062,25 @@
} }
}") }")
(define_insn "absdi2" (define_insn_and_split "absdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
(abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
(clobber (match_scratch:DI 2 "=&r,&r"))] (clobber (match_scratch:DI 2 "=&r,&r"))]
"TARGET_POWERPC64" "TARGET_POWERPC64"
"sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0" "#"
[(set_attr "length" "12")]) "&& reload_completed"
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
(clobber (match_scratch:DI 2 ""))]
"TARGET_POWERPC64 && reload_completed"
[(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
(set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
"") "")
(define_insn "*nabsdi2" (define_insn_and_split "*nabsdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
(neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
(clobber (match_scratch:DI 2 "=&r,&r"))] (clobber (match_scratch:DI 2 "=&r,&r"))]
"TARGET_POWERPC64" "TARGET_POWERPC64"
"sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2" "#"
[(set_attr "length" "12")]) "&& reload_completed"
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))))
(clobber (match_scratch:DI 2 ""))]
"TARGET_POWERPC64 && reload_completed"
[(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
(set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
...@@ -8207,52 +8187,68 @@ ...@@ -8207,52 +8187,68 @@
(define_insn_and_split "trunctfsf2" (define_insn_and_split "trunctfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))] (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
(clobber (match_scratch:DF 2 "=f"))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#" "#"
"" "&& reload_completed"
[(set (match_dup 2) [(set (match_dup 2)
(float_truncate:DF (match_dup 1))) (float_truncate:DF (match_dup 1)))
(set (match_dup 0) (set (match_dup 0)
(float_truncate:SF (match_dup 2)))] (float_truncate:SF (match_dup 2)))]
" "")
{
operands[2] = gen_reg_rtx (DFmode);
}")
(define_expand "floatditf2" (define_insn_and_split "floatditf2"
[(set (match_operand:TF 0 "gpc_reg_operand" "=f")
(float:TF (match_operand:DI 1 "gpc_reg_operand" "f")))
(clobber (match_scratch:DF 2 "=f"))]
"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
"&& reload_completed"
[(set (match_dup 2) [(set (match_dup 2)
(float:DF (match_operand:DI 1 "gpc_reg_operand" ""))) (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))
(set (match_operand:TF 0 "gpc_reg_operand" "") (set (match_operand:TF 0 "gpc_reg_operand" "")
(float_extend:TF (match_dup 2)))] (float_extend:TF (match_dup 2)))]
"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 "")
&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"{ operands[2] = gen_reg_rtx (DFmode); }")
(define_expand "floatsitf2" (define_insn_and_split "floatsitf2"
[(set (match_operand:TF 0 "gpc_reg_operand" "=f")
(float:TF (match_operand:SI 1 "gpc_reg_operand" "f")))
(clobber (match_scratch:DF 2 "=f"))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
"&& reload_completed"
[(set (match_dup 2) [(set (match_dup 2)
(float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
(set (match_operand:TF 0 "gpc_reg_operand" "") (set (match_operand:TF 0 "gpc_reg_operand" "")
(float_extend:TF (match_dup 2)))] (float_extend:TF (match_dup 2)))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "")
"{ operands[2] = gen_reg_rtx (DFmode); }")
(define_expand "fix_trunctfdi2" (define_insn_and_split "fix_trunctfdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=f")
(fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))]
"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
"&& reload_completed"
[(set (match_dup 2) [(set (match_dup 2)
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" ""))) (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
(set (match_operand:DI 0 "gpc_reg_operand" "") (set (match_operand:DI 0 "gpc_reg_operand" "")
(fix:SI (match_dup 2)))] (fix:SI (match_dup 2)))]
"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 "")
&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"{ operands[2] = gen_reg_rtx (DFmode); }")
(define_expand "fix_trunctfsi2" (define_insn_and_split "fix_trunctfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=f")
(fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
"&& reload_completed"
[(set (match_dup 2) [(set (match_dup 2)
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" ""))) (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
(set (match_operand:SI 0 "gpc_reg_operand" "") (set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_dup 2)))] (fix:SI (match_dup 2)))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "")
"{ operands[2] = gen_reg_rtx (DFmode); }")
(define_insn "negtf2" (define_insn "negtf2"
[(set (match_operand:TF 0 "gpc_reg_operand" "=f") [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
......
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