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riscv-gcc-1
Commit e970b4b0 by Andreas Krebbel Committed by Andreas Krebbel
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S/390: Make constant checking more strict 

gcc/ChangeLog:

2015-12-02  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/predicates.md (const_mask_operand): New predicate.
	* config/s390/s390-builtins.def: Set a smaller bitmask for a few builtins.
	* config/s390/vector.md: Change predicate from immediate_operand
	to either const_int_operand or const_mask_operand.  Add special
	insn conditions on patterns which have to exclude certain values.
	* config/s390/vx-builtins.md: Likewise.

From-SVN: r231159
parent 8eb1b59b
Showing with 26 additions and 12 deletions
gcc/ChangeLog
2015-12-02 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/predicates.md (const_mask_operand): New predicate.
* config/s390/s390-builtins.def: Set a smaller bitmask for a few builtins.
* config/s390/vector.md: Change predicate from immediate_operand
to either const_int_operand or const_mask_operand. Add special
insn conditions on patterns which have to exclude certain values.
* config/s390/vx-builtins.md: Likewise.
2015-12-02 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/vector.md ("*vec_set<mode>"): Change shift count
mode from DI to SI.
gcc/config/s390/predicates.md
......@@ -34,6 +34,11 @@
(and (match_code "const_int, const_double,const_vector")
(match_test "op == CONSTM1_RTX (mode)")))
;; Return true if OP is a 4 bit mask operand
(define_predicate "const_mask_operand"
(and (match_code "const_int")
(match_test "UINTVAL (op) < 16")))
;; Return true if OP is constant.
(define_special_predicate "consttable_operand"
......
gcc/config/s390/s390-builtins.def
......@@ -2470,15 +2470,15 @@ OB_DEF (s390_vec_ctd, s390_vec_ctd_s64, s390_vec_ctd_u64,
OB_DEF_VAR (s390_vec_ctd_s64, s390_vec_ctd_s64, O2_U5, BT_OV_V2DF_V2DI_INT) /* vcdgb */
OB_DEF_VAR (s390_vec_ctd_u64, s390_vec_ctd_u64, O2_U5, BT_OV_V2DF_UV2DI_INT) /* vcdlgb */
B_DEF (s390_vec_ctd_s64, vec_ctd_s64, 0, B_VX, O2_U5, BT_FN_V2DF_V2DI_INT) /* vcdgb */
B_DEF (s390_vec_ctd_u64, vec_ctd_u64, 0, B_VX, O2_U5, BT_FN_V2DF_UV2DI_INT) /* vcdlgb */
B_DEF (s390_vcdgb, vec_di_to_df_s64, 0, B_VX, O2_U5, BT_FN_V2DF_V2DI_INT)
B_DEF (s390_vcdlgb, vec_di_to_df_u64, 0, B_VX, O2_U5, BT_FN_V2DF_UV2DI_INT)
B_DEF (s390_vec_ctsl, vec_ctsl, 0, B_VX, O2_U5, BT_FN_V2DI_V2DF_INT) /* vcgdb */
B_DEF (s390_vec_ctul, vec_ctul, 0, B_VX, O2_U5, BT_FN_UV2DI_V2DF_INT) /* vclgdb */
B_DEF (s390_vcgdb, vec_df_to_di_s64, 0, B_VX, O2_U5, BT_FN_V2DI_V2DF_INT)
B_DEF (s390_vclgdb, vec_df_to_di_u64, 0, B_VX, O2_U5, BT_FN_UV2DI_V2DF_INT)
B_DEF (s390_vfidb, vfidb, 0, B_VX, O2_U4 | O3_U4, BT_FN_V2DF_V2DF_UCHAR_UCHAR)
B_DEF (s390_vec_ctd_s64, vec_ctd_s64, 0, B_VX, O2_U3, BT_FN_V2DF_V2DI_INT) /* vcdgb */
B_DEF (s390_vec_ctd_u64, vec_ctd_u64, 0, B_VX, O2_U3, BT_FN_V2DF_UV2DI_INT) /* vcdlgb */
B_DEF (s390_vcdgb, vec_di_to_df_s64, 0, B_VX, O2_U3, BT_FN_V2DF_V2DI_INT) /* vcdgb */
B_DEF (s390_vcdlgb, vec_di_to_df_u64, 0, B_VX, O2_U3, BT_FN_V2DF_UV2DI_INT) /* vcdlgb */
B_DEF (s390_vec_ctsl, vec_ctsl, 0, B_VX, O2_U3, BT_FN_V2DI_V2DF_INT) /* vcgdb */
B_DEF (s390_vec_ctul, vec_ctul, 0, B_VX, O2_U3, BT_FN_UV2DI_V2DF_INT) /* vclgdb */
B_DEF (s390_vcgdb, vec_df_to_di_s64, 0, B_VX, O2_U3, BT_FN_V2DI_V2DF_INT) /* vcgdb */
B_DEF (s390_vclgdb, vec_df_to_di_u64, 0, B_VX, O2_U3, BT_FN_UV2DI_V2DF_INT) /* vclgdb */
B_DEF (s390_vfidb, vfidb, 0, B_VX, O2_U4 | O3_U3, BT_FN_V2DF_V2DF_UCHAR_UCHAR)
B_DEF (s390_vec_ld2f, vec_ld2f, 0, B_VX, 0, BT_FN_V2DF_FLTCONSTPTR) /* vldeb */
B_DEF (s390_vec_st2f, vec_st2f, 0, B_VX, 0, BT_FN_VOID_V2DF_FLTPTR) /* vledb */
B_DEF (s390_vfmadb, fmav2df4, 0, B_VX, 0, BT_FN_V2DF_V2DF_V2DF_V2DF)
......
gcc/config/s390/vector.md
......@@ -364,8 +364,8 @@
(vec_select:<non_vec>
(match_operand:V_HW 1 "register_operand" "v")
(parallel
[(match_operand:QI 2 "immediate_operand" "C")]))))]
"TARGET_VX"
[(match_operand:QI 2 "const_mask_operand" "C")]))))]
"TARGET_VX && UINTVAL (operands[2]) < GET_MODE_NUNITS (<V_HW:MODE>mode)"
"vrep<bhfgq>\t%v0,%v1,%2"
[(set_attr "op_type" "VRI")])
......@@ -1073,7 +1073,7 @@
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
(match_operand:VI_HW_QHS 2 "register_operand" "v")
(match_operand:QI 3 "immediate_operand" "C")]
(match_operand:QI 3 "const_mask_operand" "C")]
UNSPEC_VEC_VFENE))
(set (reg:CCRAW CC_REGNUM)
(unspec:CCRAW [(match_dup 1)
......
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