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Commit e855bdc0 by Jakub Jelinek Committed by Jakub Jelinek
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re PR target/81225 (ICE with -mavx512ifma -O3 -ffloat-store) 

	PR target/81225
	* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): For
	V8FI, V16FI and VI8F_256 iterators, use <store_mask_predicate> instead
	of nonimmediate_operand and <store_mask_constraint> instead of m for
	the input operand.  For V8FI iterator, always split if input is a MEM.
	For V16FI and V8SF_256 iterators, don't test if both operands are MEM
	if <mask_applied>.  For VI4F_256 iterator, use <store_mask_predicate>
	instead of register_operand and <store_mask_constraint> instead of v for
        the input operand.  Make sure both operands aren't MEMs for if not
	<mask_applied>.

	* gcc.target/i386/pr81225.c: New test.

From-SVN: r249844
parent fe32bb1b
Showing with 47 additions and 9 deletions
gcc/ChangeLog
2017-06-30 Jakub Jelinek <jakub@redhat.com>
PR target/81225
* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): For
V8FI, V16FI and VI8F_256 iterators, use <store_mask_predicate> instead
of nonimmediate_operand and <store_mask_constraint> instead of m for
the input operand. For V8FI iterator, always split if input is a MEM.
For V16FI and V8SF_256 iterators, don't test if both operands are MEM
if <mask_applied>. For VI4F_256 iterator, use <store_mask_predicate>
instead of register_operand and <store_mask_constraint> instead of v for
the input operand. Make sure both operands aren't MEMs for if not
<mask_applied>.
2017-06-30 Sylvestre Ledru <sylvestre@debian.org>
* lto-wrapper.c (copy_file) Close both file descriptors before
......
gcc/config/i386/sse.md
......@@ -7359,13 +7359,13 @@
(define_insn "vec_extract_lo_<mode><mask_name>"
[(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=<store_mask_constraint>,v")
(vec_select:<ssehalfvecmode>
(match_operand:V8FI 1 "nonimmediate_operand" "v,m")
(match_operand:V8FI 1 "<store_mask_predicate>" "v,<store_mask_constraint>")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))]
"TARGET_AVX512F
&& (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
{
if (<mask_applied> || !TARGET_AVX512VL)
if (<mask_applied> || (!TARGET_AVX512VL && !MEM_P (operands[1])))
return "vextract<shuffletype>64x4\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
else
return "#";
......@@ -7515,14 +7515,15 @@
(define_insn "vec_extract_lo_<mode><mask_name>"
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,m")
(vec_select:<ssehalfvecmode>
(match_operand:V16FI 1 "nonimmediate_operand" "vm,v")
(match_operand:V16FI 1 "<store_mask_predicate>"
"<store_mask_constraint>,v")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)
(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))]
"TARGET_AVX512F
&& <mask_mode512bit_condition>
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
&& (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
{
if (<mask_applied>)
return "vextract<shuffletype>32x8\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
......@@ -7546,11 +7547,12 @@
(define_insn "vec_extract_lo_<mode><mask_name>"
[(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,m")
(vec_select:<ssehalfvecmode>
(match_operand:VI8F_256 1 "nonimmediate_operand" "vm,v")
(match_operand:VI8F_256 1 "<store_mask_predicate>"
"<store_mask_constraint>,v")
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_AVX
&& <mask_avx512vl_condition> && <mask_avx512dq_condition>
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
&& (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
{
if (<mask_applied>)
return "vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}";
......@@ -7610,12 +7612,16 @@
"operands[1] = gen_lowpart (<ssehalfvecmode>mode, operands[1]);")
(define_insn "vec_extract_lo_<mode><mask_name>"
[(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=<store_mask_constraint>")
[(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
"=<store_mask_constraint>,v")
(vec_select:<ssehalfvecmode>
(match_operand:VI4F_256 1 "register_operand" "v")
(match_operand:VI4F_256 1 "<store_mask_predicate>"
"v,<store_mask_constraint>")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))]
"TARGET_AVX && <mask_avx512vl_condition> && <mask_avx512dq_condition>"
"TARGET_AVX
&& <mask_avx512vl_condition> && <mask_avx512dq_condition>
&& (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
{
if (<mask_applied>)
return "vextract<shuffletype>32x4\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
......
gcc/testsuite/ChangeLog
2017-06-30 Jakub Jelinek <jakub@redhat.com>
PR target/81225
* gcc.target/i386/pr81225.c: New test.
2017-06-30 Nathan Sidwell <nathan@acm.org>
* g++.dg/concepts/memfun-err.C: Adjust diagnostics.
......
gcc/testsuite/gcc.target/i386/pr81225.c 0 → 100644
/* PR target/81225 */
/* { dg-do compile } */
/* { dg-options "-mavx512ifma -O3 -ffloat-store" } */
long a[24];
float b[4], c[24];
int d;
void
foo ()
{
for (d = 0; d < 24; d++)
c[d] = (float) d ? : b[a[d]];
}
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