sse.md (V16): New mode iterator.

	* config/i386/sse.md (V16): New mode iterator.
	(VI1, VI8): Ditto.
	(AVXMODEQI, AVXMODEDI): Remove.
	(sse2, sse3): New mode attribute.
	(mov<mode>): Use V16 mode iterator.
	(*mov<mode>_internal): Merge with *avx_mov<mode>_internal.
	(push<mode>1): Use V16 mode iterator.
	(movmisalign<mode>): Ditto.
	(<sse>_movu<ssemodesuffix><avxmodesuffix>): Merge from
	<sse>_movu<ssemodesuffix> and avx_movu<ssemodesuffix><avxmodesuffix>.
	(*<sse>_movu<ssemodesuffix><avxmodesuffix>): Merge from
	*<sse>_movu<ssemodesuffix> and *avx_movu<ssemodesuffix><avxmodesuffix>.
	(<sse2>_movdqu<avxmodesuffix>): Merge from sse2_movdqu and
	avx_movdqu<avxmodesuffix>.
	(*<sse2>_movdqu<avxmodesuffix>): Merge from *sse2_movdqu and
	*avx_movdqu<avxmodesuffix>.
	(<sse3>_lddqu<avxmodesuffix>) Merge from sse3_lddqu and
	avx_lddqu<avxmodesuffix>.
	(<sse>_movnt<mode>): Merge with avx_movnt<AVXMODEF2P:mode>.
	(<sse2>_movnt<mode>): Merge from sse2_movntv2di and
	avx_movnt<AVXMODEDI:mode>.
	* config/i386/i386.c (ix86_expand_vector_move_misalign): Update for
	renamed sse_movups, sse2_movupd and sse2_movdqu patterns.

testsuite/ChangeLog:

	* gcc.target/i386/avx256-unaligned-load-1.c: Update scan patterns.
	* gcc.target/i386/avx256-unaligned-load-2.c: Ditto.
	* gcc.target/i386/avx256-unaligned-load-3.c: Ditto.
	* gcc.target/i386/avx256-unaligned-store-1.c: Ditto.
	* gcc.target/i386/avx256-unaligned-store-2.c: Ditto.
	* gcc.target/i386/avx256-unaligned-store-3.c: Ditto.

From-SVN: r172580

gcc/ChangeLog

+2011-04-16  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/sse.md (V16): New mode iterator.
+	(VI1, VI8): Ditto.
+	(AVXMODEQI, AVXMODEDI): Remove.
+	(sse2, sse3): New mode attribute.
+	(mov<mode>): Use V16 mode iterator.
+	(*mov<mode>_internal): Merge with *avx_mov<mode>_internal.
+	(push<mode>1): Use V16 mode iterator.
+	(movmisalign<mode>): Ditto.
+	(<sse>_movu<ssemodesuffix><avxmodesuffix>): Merge from
+	<sse>_movu<ssemodesuffix> and avx_movu<ssemodesuffix><avxmodesuffix>.
+	(*<sse>_movu<ssemodesuffix><avxmodesuffix>): Merge from
+	*<sse>_movu<ssemodesuffix> and *avx_movu<ssemodesuffix><avxmodesuffix>.
+	(<sse2>_movdqu<avxmodesuffix>): Merge from sse2_movdqu and
+	avx_movdqu<avxmodesuffix>.
+	(*<sse2>_movdqu<avxmodesuffix>): Merge from *sse2_movdqu and
+	*avx_movdqu<avxmodesuffix>.
+	(<sse3>_lddqu<avxmodesuffix>) Merge from sse3_lddqu and
+	avx_lddqu<avxmodesuffix>.
+	(<sse>_movnt<mode>): Merge with avx_movnt<AVXMODEF2P:mode>.
+	(<sse2>_movnt<mode>): Merge from sse2_movntv2di and
+	avx_movnt<AVXMODEDI:mode>.
+	* config/i386/i386.c (ix86_expand_vector_move_misalign): Update for
+	renamed sse_movups, sse2_movupd and sse2_movdqu patterns.
+
 2011-04-16  Bernd Schmidt  <bernds@codesourcery.com>
 
 	PR target/48629
@@ -24,8 +50,8 @@
 	* gimple.h (enum gf_mask): Add GF_CALL_ALLOCA_FOR_VAR.
 	(gimple_call_set_alloca_for_var): New inline function.
 	(gimple_call_alloca_for_var_p): Ditto.
-	* gimple.c (gimple_build_call_from_tree): Remember CALL_ALLOCA_FOR_VAR_P
-	state.
+	* gimple.c (gimple_build_call_from_tree): Remember
+	CALL_ALLOCA_FOR_VAR_P state.
 	* cfgexpand.c (expand_call_stmt): Restore CALL_ALLOCA_FOR_VAR_P state.
 
 	* tree-inline.c (inline_forbidden_p_stmt): Don't reject alloca
@@ -87,7 +113,7 @@
 	-fsched-pressure.
 
 2011-04-15  Georg-Johann Lay  <avr@gjlay.de>
-	
+
 	* config/avr/avr.md ("rotl<mode>3",mode=HIDI): Use match_dup
 	instead of match_operand for operand 3.
 

gcc/config/i386/i386.c

@@ -15769,12 +15769,12 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
 		{
 		  op0 = gen_lowpart (V4SFmode, op0);
 		  op1 = gen_lowpart (V4SFmode, op1);
-		  emit_insn (gen_avx_movups (op0, op1));
+		  emit_insn (gen_sse_movups (op0, op1));
 		  return;
 		}
 	      op0 = gen_lowpart (V16QImode, op0);
 	      op1 = gen_lowpart (V16QImode, op1);
-	      emit_insn (gen_avx_movdqu (op0, op1));
+	      emit_insn (gen_sse2_movdqu (op0, op1));
 	      break;
 	    case 32:
 	      op0 = gen_lowpart (V32QImode, op0);
@@ -15792,7 +15792,7 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
 	  switch (mode)
 	    {
 	    case V4SFmode:
-	      emit_insn (gen_avx_movups (op0, op1));
+	      emit_insn (gen_sse_movups (op0, op1));
 	      break;
 	    case V8SFmode:
 	      ix86_avx256_split_vector_move_misalign (op0, op1);
@@ -15802,10 +15802,10 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
 		{
 		  op0 = gen_lowpart (V4SFmode, op0);
 		  op1 = gen_lowpart (V4SFmode, op1);
-		  emit_insn (gen_avx_movups (op0, op1));
+		  emit_insn (gen_sse_movups (op0, op1));
 		  return;
 		}
-	      emit_insn (gen_avx_movupd (op0, op1));
+	      emit_insn (gen_sse2_movupd (op0, op1));
 	      break;
 	    case V4DFmode:
 	      ix86_avx256_split_vector_move_misalign (op0, op1);

gcc/testsuite/ChangeLog

+2011-04-16  Uros Bizjak  <ubizjak@gmail.com>
+
+	* gcc.target/i386/avx256-unaligned-load-1.c: Update scan patterns.
+	* gcc.target/i386/avx256-unaligned-load-2.c: Ditto.
+	* gcc.target/i386/avx256-unaligned-load-3.c: Ditto.
+	* gcc.target/i386/avx256-unaligned-store-1.c: Ditto.
+	* gcc.target/i386/avx256-unaligned-store-2.c: Ditto.
+	* gcc.target/i386/avx256-unaligned-store-3.c: Ditto.
+
 2011-04-15  Jason Merrill  <jason@redhat.com>
 
 	* g++.dg/cpp0x/range-for17.C: New.
@@ -22,14 +31,14 @@
 2011-04-15  Nicola Pero  <nicola.pero@meta-innovation.com>
 
 	* objc.dg/naming-4.m: Updated.
-	* objc.dg/naming-5.m: Updated.	
+	* objc.dg/naming-5.m: Updated.
 	* objc.dg/naming-6.m: New.
-	* objc.dg/naming-7.m: New.	
+	* objc.dg/naming-7.m: New.
 	* obj-c++.dg/naming-1.mm: Updated.
 	* obj-c++.dg/naming-2.mm: Updated.
 	* obj-c++.dg/naming-3.mm: New.
 	* obj-c++.dg/naming-4.mm: New.
-	
+
 2011-04-15  Jerry DeLisle  <jvdelisle@gcc.gnu.org>
 
 	PR libgfortran/48589

gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c

@@ -15,5 +15,5 @@ avx_test (void)
 }
 
 /* { dg-final { scan-assembler-not "\\*avx_movups256/1" } } */
-/* { dg-final { scan-assembler "\\*avx_movups/1" } } */
+/* { dg-final { scan-assembler "\\*sse_movups/1" } } */
 /* { dg-final { scan-assembler "vinsertf128" } } */

gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c

@@ -25,5 +25,5 @@ avx_test (void)
 }
 
 /* { dg-final { scan-assembler-not "\\*avx_movdqu256/1" } } */
-/* { dg-final { scan-assembler "\\*avx_movdqu/1" } } */
+/* { dg-final { scan-assembler "\\*sse2_movdqu/1" } } */
 /* { dg-final { scan-assembler "vinsertf128" } } */

gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c

@@ -15,5 +15,5 @@ avx_test (void)
 }
 
 /* { dg-final { scan-assembler-not "\\*avx_movupd256/1" } } */
-/* { dg-final { scan-assembler "\\*avx_movupd/1" } } */
+/* { dg-final { scan-assembler "\\*sse2_movupd/1" } } */
 /* { dg-final { scan-assembler "vinsertf128" } } */

gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c

@@ -18,5 +18,5 @@ avx_test (void)
 }
 
 /* { dg-final { scan-assembler-not "\\*avx_movups256/2" } } */
-/* { dg-final { scan-assembler "movups.*\\*avx_movv4sf_internal/3" } } */
+/* { dg-final { scan-assembler "vmovups.*\\*movv4sf_internal/3" } } */
 /* { dg-final { scan-assembler "vextractf128" } } */

gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c

@@ -25,5 +25,5 @@ avx_test (void)
 }
 
 /* { dg-final { scan-assembler-not "\\*avx_movdqu256/2" } } */
-/* { dg-final { scan-assembler "movdqu.*\\*avx_movv16qi_internal/3" } } */
+/* { dg-final { scan-assembler "vmovdqu.*\\*movv16qi_internal/3" } } */
 /* { dg-final { scan-assembler "vextractf128" } } */

gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c

@@ -18,5 +18,5 @@ avx_test (void)
 }
 
 /* { dg-final { scan-assembler-not "\\*avx_movupd256/2" } } */
-/* { dg-final { scan-assembler "movupd.*\\*avx_movv2df_internal/3" } } */
+/* { dg-final { scan-assembler "vmovupd.*\\*movv2df_internal/3" } } */
 /* { dg-final { scan-assembler "vextractf128" } } */