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riscv-gcc-1
Commit e8030e8c by Richard Kenner
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Consistently use `&' in constraint of MATCH_SCRATCH. 

Always use a reg as 4th arg of dmac/fmac even if ignored by insn.
Uses of `b' as a constraint in multi-word reload patterns should be `c'.

From-SVN: r2900
parent 3c243b51
Showing with 27 additions and 27 deletions
gcc/config/a29k/a29k.md
...@@ -185,7 +185,7 @@ ...@@ -185,7 +185,7 @@
(define_insn "" (define_insn ""
[(call (match_operand:SI 0 "memory_operand" "m") [(call (match_operand:SI 0 "memory_operand" "m")
(match_operand 1 "" "")) (match_operand 1 "" ""))
(clobber (match_scratch:SI 2 "=l"))] (clobber (match_scratch:SI 2 "=&l"))]
"GET_CODE (XEXP (operands[0], 0)) != CONST_INT" "GET_CODE (XEXP (operands[0], 0)) != CONST_INT"
"calli lr0,%0%#" "calli lr0,%0%#"
[(set_attr "type" "call")]) [(set_attr "type" "call")])
...@@ -193,7 +193,7 @@ ...@@ -193,7 +193,7 @@
(define_insn "" (define_insn ""
[(call (mem:SI (match_operand:SI 0 "call_operand" "i")) [(call (mem:SI (match_operand:SI 0 "call_operand" "i"))
(match_operand:SI 1 "general_operand" "g")) (match_operand:SI 1 "general_operand" "g"))
(clobber (match_scratch:SI 2 "=l"))] (clobber (match_scratch:SI 2 "=&l"))]
"" ""
"call lr0,%F0" "call lr0,%F0"
[(set_attr "type" "call")]) [(set_attr "type" "call")])
...@@ -202,7 +202,7 @@ ...@@ -202,7 +202,7 @@
[(set (match_operand 0 "gpc_reg_operand" "=r") [(set (match_operand 0 "gpc_reg_operand" "=r")
(call (match_operand:SI 1 "memory_operand" "m") (call (match_operand:SI 1 "memory_operand" "m")
(match_operand 2 "" ""))) (match_operand 2 "" "")))
(clobber (match_scratch:SI 3 "=l"))] (clobber (match_scratch:SI 3 "=&l"))]
"GET_CODE (XEXP (operands[1], 0)) != CONST_INT" "GET_CODE (XEXP (operands[1], 0)) != CONST_INT"
"calli lr0,%1%#" "calli lr0,%1%#"
[(set_attr "type" "call")]) [(set_attr "type" "call")])
...@@ -211,7 +211,7 @@ ...@@ -211,7 +211,7 @@
[(set (match_operand 0 "gpc_reg_operand" "=r") [(set (match_operand 0 "gpc_reg_operand" "=r")
(call (mem:SI (match_operand:SI 1 "call_operand" "i")) (call (mem:SI (match_operand:SI 1 "call_operand" "i"))
(match_operand:SI 2 "general_operand" "g"))) (match_operand:SI 2 "general_operand" "g")))
(clobber (match_scratch:SI 3 "=l"))] (clobber (match_scratch:SI 3 "=&l"))]
"" ""
"call lr0,%F1" "call lr0,%F1"
[(set_attr "type" "call")]) [(set_attr "type" "call")])
...@@ -384,7 +384,7 @@ ...@@ -384,7 +384,7 @@
"TARGET_29050" "TARGET_29050"
"@ "@
dadd %0,%1,%2 dadd %0,%1,%2
dmac 8,%0,%1,0" dmac 8,%0,%1,%1"
[(set_attr "type" "fadd,dam")]) [(set_attr "type" "fadd,dam")])
;; DDIV ;; DDIV
...@@ -508,7 +508,7 @@ ...@@ -508,7 +508,7 @@
(minus:DF (neg:DF (match_operand:DF 1 "register_operand" "r")) (minus:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
(match_operand:DF 2 "register_operand" "0")))] (match_operand:DF 2 "register_operand" "0")))]
"TARGET_29050" "TARGET_29050"
"dmac 11,%0,%1,0" "dmac 11,%0,%1,%1"
[(set_attr "type" "dam")]) [(set_attr "type" "dam")])
(define_insn "" (define_insn ""
...@@ -516,7 +516,7 @@ ...@@ -516,7 +516,7 @@
(neg:DF (plus:DF (match_operand:DF 1 "register_operand" "%r") (neg:DF (plus:DF (match_operand:DF 1 "register_operand" "%r")
(match_operand:DF 2 "register_operand" "0"))))] (match_operand:DF 2 "register_operand" "0"))))]
"TARGET_29050" "TARGET_29050"
"dmac 11,%0,%1,0" "dmac 11,%0,%1,%1"
[(set_attr "type" "dam")]) [(set_attr "type" "dam")])
(define_insn "" (define_insn ""
...@@ -527,7 +527,7 @@ ...@@ -527,7 +527,7 @@
"@ "@
cpeq %2,gr1,gr1\;xor %0,%1,%2 cpeq %2,gr1,gr1\;xor %0,%1,%2
cpeq %2,gr1,gr1\;xor %0,%1,%2\;sll %L0,%L1,0 cpeq %2,gr1,gr1\;xor %0,%1,%2\;sll %L0,%L1,0
dmac 13,%0,%1,0" dmac 13,%0,%1,%1"
[(set_attr "type" "multi,multi,dam")]) [(set_attr "type" "multi,multi,dam")])
;; DMUL ;; DMUL
...@@ -579,8 +579,8 @@ ...@@ -579,8 +579,8 @@
"TARGET_29050" "TARGET_29050"
"@ "@
dsub %0,%1,%2 dsub %0,%1,%2
dmac 9,%0,%2,0 dmac 9,%0,%2,%2
dmac 10,%0,%1,0" dmac 10,%0,%1,%1"
[(set_attr "type" "fadd,dam,dam")]) [(set_attr "type" "fadd,dam,dam")])
;; EXBYTE ;; EXBYTE
...@@ -749,7 +749,7 @@ ...@@ -749,7 +749,7 @@
"TARGET_29050" "TARGET_29050"
"@ "@
fadd %0,%1,%2 fadd %0,%1,%2
fmac 8,%0,%1,0" fmac 8,%0,%1,%1"
[(set_attr "type" "fadd,fam")]) [(set_attr "type" "fadd,fam")])
;; FDIV ;; FDIV
...@@ -821,7 +821,7 @@ ...@@ -821,7 +821,7 @@
(minus:SF (neg:SF (match_operand:SF 1 "register_operand" "%r")) (minus:SF (neg:SF (match_operand:SF 1 "register_operand" "%r"))
(match_operand:SF 2 "register_operand" "0")))] (match_operand:SF 2 "register_operand" "0")))]
"TARGET_29050" "TARGET_29050"
"fmac 11,%0,%1,0" "fmac 11,%0,%1,%1"
[(set_attr "type" "fam")]) [(set_attr "type" "fam")])
(define_insn "" (define_insn ""
...@@ -829,7 +829,7 @@ ...@@ -829,7 +829,7 @@
(neg:SF (plus:SF (match_operand:SF 1 "register_operand" "%r") (neg:SF (plus:SF (match_operand:SF 1 "register_operand" "%r")
(match_operand:SF 2 "register_operand" "0"))))] (match_operand:SF 2 "register_operand" "0"))))]
"TARGET_29050" "TARGET_29050"
"fmac 11,%0,%1,0" "fmac 11,%0,%1,%1"
[(set_attr "type" "fam")]) [(set_attr "type" "fam")])
(define_insn "" (define_insn ""
...@@ -839,7 +839,7 @@ ...@@ -839,7 +839,7 @@
"TARGET_29050" "TARGET_29050"
"@ "@
cpeq %2,gr1,gr1\;xor %0,%1,%2 cpeq %2,gr1,gr1\;xor %0,%1,%2
fmac 13,%0,%1,0" fmac 13,%0,%1,%1"
[(set_attr "type" "multi,fam")]) [(set_attr "type" "multi,fam")])
;; FMUL ;; FMUL
...@@ -891,8 +891,8 @@ ...@@ -891,8 +891,8 @@
"TARGET_29050" "TARGET_29050"
"@ "@
fsub %0,%1,%2 fsub %0,%1,%2
fmac 9,%0,%2,0 fmac 9,%0,%2,%2
fmac 10,%0,%1,0" fmac 10,%0,%1,%1"
[(set_attr "type" "fadd,fam,fam")]) [(set_attr "type" "fadd,fam,fam")])
;; INBYTE ;; INBYTE
...@@ -1006,7 +1006,7 @@ ...@@ -1006,7 +1006,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))) (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))
(clobber (match_scratch:PSI 2 "=b"))] (clobber (match_scratch:PSI 2 "=&b"))]
"TARGET_DW_ENABLE" "TARGET_DW_ENABLE"
"load 0,17,%0,%1" "load 0,17,%0,%1"
[(set_attr "type" "load")]) [(set_attr "type" "load")])
...@@ -1014,7 +1014,7 @@ ...@@ -1014,7 +1014,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:HI 0 "gpc_reg_operand" "=r") [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
(sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))) (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))
(clobber (match_scratch:PSI 2 "=b"))] (clobber (match_scratch:PSI 2 "=&b"))]
"TARGET_DW_ENABLE" "TARGET_DW_ENABLE"
"load 0,17,%0,%1" "load 0,17,%0,%1"
[(set_attr "type" "load")]) [(set_attr "type" "load")])
...@@ -1022,7 +1022,7 @@ ...@@ -1022,7 +1022,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))) (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))
(clobber (match_scratch:PSI 2 "=b"))] (clobber (match_scratch:PSI 2 "=&b"))]
"TARGET_DW_ENABLE" "TARGET_DW_ENABLE"
"load 0,18,%0,%1" "load 0,18,%0,%1"
[(set_attr "type" "load")]) [(set_attr "type" "load")])
...@@ -1435,7 +1435,7 @@ ...@@ -1435,7 +1435,7 @@
(define_insn "" (define_insn ""
[(set (match_operand 0 "memory_operand" "=m") [(set (match_operand 0 "memory_operand" "=m")
(match_operand 1 "gpc_reg_operand" "r")) (match_operand 1 "gpc_reg_operand" "r"))
(clobber (match_scratch:PSI 2 "=c"))] (clobber (match_scratch:PSI 2 "=&c"))]
"!TARGET_NO_STOREM_BUG "!TARGET_NO_STOREM_BUG
&& GET_MODE (operands[0]) == GET_MODE (operands[1]) && GET_MODE (operands[0]) == GET_MODE (operands[1])
&& GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD" && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
...@@ -1446,7 +1446,7 @@ ...@@ -1446,7 +1446,7 @@
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (match_operand:SI 1 "memory_operand" "=m") [(set (match_operand:SI 1 "memory_operand" "=m")
(match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r"))
(clobber (match_scratch:PSI 3 "=c"))])] (clobber (match_scratch:PSI 3 "=&c"))])]
"!TARGET_NO_STOREM_BUG" "!TARGET_NO_STOREM_BUG"
"mtsrim cr,%V0\;storem 0,0,%2,%1" "mtsrim cr,%V0\;storem 0,0,%2,%1"
[(set_attr "type" "multi")]) [(set_attr "type" "multi")])
...@@ -2410,42 +2410,42 @@ ...@@ -2410,42 +2410,42 @@
(define_expand "reload_indf" (define_expand "reload_indf"
[(parallel [(set (match_operand:DF 0 "register_operand" "=r") [(parallel [(set (match_operand:DF 0 "register_operand" "=r")
(match_operand:DF 1 "reload_memory_operand" "m")) (match_operand:DF 1 "reload_memory_operand" "m"))
(clobber (match_operand:PSI 2 "register_operand" "=&b"))])] (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
"" ""
"") "")
(define_expand "reload_outdf" (define_expand "reload_outdf"
[(parallel [(set (match_operand:DF 0 "reload_memory_operand" "=m") [(parallel [(set (match_operand:DF 0 "reload_memory_operand" "=m")
(match_operand:DF 1 "register_operand" "r")) (match_operand:DF 1 "register_operand" "r"))
(clobber (match_operand:PSI 2 "register_operand" "=&b"))])] (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
"" ""
"") "")
(define_expand "reload_indi" (define_expand "reload_indi"
[(parallel [(set (match_operand:DI 0 "register_operand" "=r") [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "reload_memory_operand" "m")) (match_operand:DI 1 "reload_memory_operand" "m"))
(clobber (match_operand:PSI 2 "register_operand" "=&b"))])] (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
"" ""
"") "")
(define_expand "reload_outdi" (define_expand "reload_outdi"
[(parallel [(set (match_operand:DI 0 "reload_memory_operand" "=m") [(parallel [(set (match_operand:DI 0 "reload_memory_operand" "=m")
(match_operand:DI 1 "register_operand" "r")) (match_operand:DI 1 "register_operand" "r"))
(clobber (match_operand:PSI 2 "register_operand" "=&b"))])] (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
"" ""
"") "")
(define_expand "reload_inti" (define_expand "reload_inti"
[(parallel [(set (match_operand:TI 0 "register_operand" "=r") [(parallel [(set (match_operand:TI 0 "register_operand" "=r")
(match_operand:TI 1 "reload_memory_operand" "m")) (match_operand:TI 1 "reload_memory_operand" "m"))
(clobber (match_operand:PSI 2 "register_operand" "=&b"))])] (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
"" ""
"") "")
(define_expand "reload_outti" (define_expand "reload_outti"
[(parallel [(set (match_operand:TI 0 "reload_memory_operand" "=m") [(parallel [(set (match_operand:TI 0 "reload_memory_operand" "=m")
(match_operand:TI 1 "register_operand" "r")) (match_operand:TI 1 "register_operand" "r"))
(clobber (match_operand:PSI 2 "register_operand" "=&b"))])] (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
"" ""
"") "")
......
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