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Commit e7c6980e by Anatoly Sokolov Committed by Anatoly Sokolov
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[MCORE] Hookize GO_IF_LEGITIMATE_ADDRESS 

From-SVN: r229561
parent 334b4842
Showing with 85 additions and 85 deletions
gcc/ChangeLog
2015-08-29 Anatoly Sokolov <aesok@post.ru>
* config/mcore/mcore.h (REG_OK_FOR_BASE_P, REG_OK_FOR_INDEX_P,
BASE_REGISTER_RTX_P, INDEX_REGISTER_RTX_P,
GO_IF_LEGITIMATE_ADDRESS): Remove macros.
* config/mcore/mcore.c (mcore_reg_ok_for_base_p,
mcore_base_register_rtx_p, mcore_legitimate_index_p,
mcore_legitimate_address_p): New functions.
(TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P): Define.
2015-10-29 Jeff Law <law@redhat.com>
* tree-ssa-scopedtables.h (const_and_copies): Remove invalidate
gcc/config/mcore/mcore.c
......@@ -139,6 +139,8 @@ static void mcore_trampoline_init (rtx, tree, rtx);
static bool mcore_warn_func_return (tree);
static void mcore_option_override (void);
static bool mcore_legitimate_constant_p (machine_mode, rtx);
static bool mcore_legitimate_address_p (machine_mode, rtx, bool,
addr_space_t);
/* MCore specific attributes. */
......@@ -226,6 +228,8 @@ static const struct attribute_spec mcore_attribute_table[] =
#undef TARGET_LEGITIMATE_CONSTANT_P
#define TARGET_LEGITIMATE_CONSTANT_P mcore_legitimate_constant_p
#undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P
#define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P mcore_legitimate_address_p
#undef TARGET_WARN_FUNC_RETURN
#define TARGET_WARN_FUNC_RETURN mcore_warn_func_return
......@@ -3179,3 +3183,74 @@ mcore_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
return GET_CODE (x) != CONST_DOUBLE;
}
/* Helper function for `mcore_legitimate_address_p'. */
static bool
mcore_reg_ok_for_base_p (const_rtx reg, bool strict_p)
{
if (strict_p)
return REGNO_OK_FOR_BASE_P (REGNO (reg));
else
return (REGNO (reg) <= 16 || !HARD_REGISTER_P (reg));
}
static bool
mcore_base_register_rtx_p (const_rtx x, bool strict_p)
{
return REG_P(x) && mcore_reg_ok_for_base_p (x, strict_p);
}
/* A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60,
and for DI is 0..56 because we use two SI loads, etc. */
static bool
mcore_legitimate_index_p (machine_mode mode, const_rtx op)
{
if (CONST_INT_P (op))
{
if (GET_MODE_SIZE (mode) >= 4
&& (((unsigned HOST_WIDE_INT) INTVAL (op)) % 4) == 0
&& ((unsigned HOST_WIDE_INT) INTVAL (op))
<= (unsigned HOST_WIDE_INT) 64 - GET_MODE_SIZE (mode))
return true;
if (GET_MODE_SIZE (mode) == 2
&& (((unsigned HOST_WIDE_INT) INTVAL (op)) % 2) == 0
&& ((unsigned HOST_WIDE_INT) INTVAL (op)) <= 30)
return true;
if (GET_MODE_SIZE (mode) == 1
&& ((unsigned HOST_WIDE_INT) INTVAL (op)) <= 15)
return true;
}
return false;
}
/* Worker function for TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P.
Allow REG
REG + disp */
static bool
mcore_legitimate_address_p (machine_mode mode, rtx x, bool strict_p,
addr_space_t as)
{
gcc_assert (ADDR_SPACE_GENERIC_P (as));
if (mcore_base_register_rtx_p (x, strict_p))
return true;
else if (GET_CODE (x) == PLUS || GET_CODE (x) == LO_SUM)
{
rtx xop0 = XEXP (x, 0);
rtx xop1 = XEXP (x, 1);
if (mcore_base_register_rtx_p (xop0, strict_p)
&& mcore_legitimate_index_p (mode, xop1))
return true;
if (mcore_base_register_rtx_p (xop1, strict_p)
&& mcore_legitimate_index_p (mode, xop0))
return true;
}
return false;
}
gcc/config/mcore/mcore.h
......@@ -529,91 +529,6 @@ extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
/* Recognize any constant value that is a valid address. */
#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
We have two alternate definitions for each of them.
The usual definition accepts all pseudo regs; the other rejects
them unless they have been allocated suitable hard regs.
The symbol REG_OK_STRICT causes the latter definition to be used. */
#ifndef REG_OK_STRICT
/* Nonzero if X is a hard reg that can be used as a base reg
or if it is a pseudo reg. */
#define REG_OK_FOR_BASE_P(X) \
(REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
/* Nonzero if X is a hard reg that can be used as an index
or if it is a pseudo reg. */
#define REG_OK_FOR_INDEX_P(X) 0
#else
/* Nonzero if X is a hard reg that can be used as a base reg. */
#define REG_OK_FOR_BASE_P(X) \
REGNO_OK_FOR_BASE_P (REGNO (X))
/* Nonzero if X is a hard reg that can be used as an index. */
#define REG_OK_FOR_INDEX_P(X) 0
#endif
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
that is a valid memory address for an instruction.
The MODE argument is the machine mode for the MEM expression
that wants to use this address.
The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
#define BASE_REGISTER_RTX_P(X) \
(GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
#define INDEX_REGISTER_RTX_P(X) \
(GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
/* Jump to LABEL if X is a valid address RTX. This must also take
REG_OK_STRICT into account when deciding about valid registers, but it uses
the above macros so we are in luck.
Allow REG
REG+disp
A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60,
and for DI is 0..56 because we use two SI loads, etc. */
#define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
do \
{ \
if (GET_CODE (OP) == CONST_INT) \
{ \
if (GET_MODE_SIZE (MODE) >= 4 \
&& (((unsigned HOST_WIDE_INT) INTVAL (OP)) % 4) == 0 \
&& ((unsigned HOST_WIDE_INT) INTVAL (OP)) \
<= (unsigned HOST_WIDE_INT) 64 - GET_MODE_SIZE (MODE)) \
goto LABEL; \
if (GET_MODE_SIZE (MODE) == 2 \
&& (((unsigned HOST_WIDE_INT) INTVAL (OP)) % 2) == 0 \
&& ((unsigned HOST_WIDE_INT) INTVAL (OP)) <= 30) \
goto LABEL; \
if (GET_MODE_SIZE (MODE) == 1 \
&& ((unsigned HOST_WIDE_INT) INTVAL (OP)) <= 15) \
goto LABEL; \
} \
} \
while (0)
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
{ \
if (BASE_REGISTER_RTX_P (X)) \
goto LABEL; \
else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \
{ \
rtx xop0 = XEXP (X,0); \
rtx xop1 = XEXP (X,1); \
if (BASE_REGISTER_RTX_P (xop0)) \
GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
if (BASE_REGISTER_RTX_P (xop1)) \
GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
} \
}
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */
#define CASE_VECTOR_MODE SImode
......
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