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riscv-gcc-1
Commit e7208ea3 by Uros Bizjak
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i386.c (iy86_option_override_internal): Update processor_alias_table for missing… 

i386.c (iy86_option_override_internal): Update processor_alias_table for missing PTA_PRFCHW and PTA_FXSR flags.

	* config/i386/i386.c (iy86_option_override_internal): Update
	processor_alias_table for missing PTA_PRFCHW and PTA_FXSR flags.  Add
	PTA_POPCNT to corei7 entry and remove PTA_SSE from athlon-4 entry.
	Do not enable SSE prefetch on non-SSE 3dNow! targets.  Enable
	TARGET_PRFCHW for TARGET_3DNOW targets.
	* config/i386/i386.md (prefetch): Enable for TARGET_PRFCHW instead
	of TARGET_3DNOW.
	(*prefetch_3dnow): Enable for TARGET_PRFCHW only.

From-SVN: r198942
parent e7413f3d
Showing with 59 additions and 46 deletions
gcc/ChangeLog
2013-05-15 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.c (iy86_option_override_internal): Update
processor_alias_table for missing PTA_PRFCHW and PTA_FXSR flags. Add
PTA_POPCNT to corei7 entry and remove PTA_SSE from athlon-4 entry.
Do not enable SSE prefetch on non-SSE 3dNow! targets. Enable
TARGET_PRFCHW for TARGET_3DNOW targets.
* config/i386/i386.md (prefetch): Enable for TARGET_PRFCHW instead
of TARGET_3DNOW.
(*prefetch_3dnow): Enable for TARGET_PRFCHW only.
2013-05-15 Andreas Schwab <schwab@suse.de> 2013-05-15 Andreas Schwab <schwab@suse.de>
* config/m68k/m68k.md (*rotlhi3_lowpart, *rotlqi3_lowpart): Name * config/m68k/m68k.md (*rotlhi3_lowpart, *rotlqi3_lowpart): Name
...@@ -132,9 +143,10 @@ ...@@ -132,9 +143,10 @@
PR lto/57038 PR lto/57038
PR lto/47375 PR lto/47375
* lto-symtab.c (lto_symtab_symbol_p): Add external symbol; weakrefs are * lto-symtab.c (lto_symtab_symbol_p): Add external symbol;
not external. weakrefs are not external.
(lto_symtab_merge_decls): Fix thinko when dealing with non-lto_symtab decls. (lto_symtab_merge_decls): Fix thinko when dealing with
non-lto_symtab decls.
(lto_symtab_merge_cgraph_nodes): Use lto_symtab_symbol_p. (lto_symtab_merge_cgraph_nodes): Use lto_symtab_symbol_p.
(lto_symtab_prevailing_decl): Get int sync with lto_symtab_symbol_p. (lto_symtab_prevailing_decl): Get int sync with lto_symtab_symbol_p.
* varpool.c (dump_varpool_node): Dump more flags. * varpool.c (dump_varpool_node): Dump more flags.
...@@ -225,7 +237,7 @@ ...@@ -225,7 +237,7 @@
2013-05-14 Joern Rennecke <joern.rennecke@embecosm.com> 2013-05-14 Joern Rennecke <joern.rennecke@embecosm.com>
* config/avr/avr.c (avr_encode_section_info): Bail out if the type * config/avr/avr.c (avr_encode_section_info): Bail out if the type
is error_mark_node. is error_mark_node.
2013-05-14 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> 2013-05-14 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
...@@ -279,11 +291,9 @@ ...@@ -279,11 +291,9 @@
PR target/56975 PR target/56975
* config/i386/cygming.h (TARGET_PECOFF): Define as true. * config/i386/cygming.h (TARGET_PECOFF): Define as true.
* config/i386/i386.h (TARGET_PECOFF): Define by default * config/i386/i386.h (TARGET_PECOFF): Define by default as false.
as false.
(PIC_OFFSET_TABLE_REGNUM): Use TARGET_PECOFF. (PIC_OFFSET_TABLE_REGNUM): Use TARGET_PECOFF.
* config/i386/i386.c (ix86_option_override_internal): * config/i386/i386.c (ix86_option_override_internal): Likewise.
Likewise.
(ix86_expand_prologue): Likewise. (ix86_expand_prologue): Likewise.
(ix86_expand_split_stack_prologue): Likewise. (ix86_expand_split_stack_prologue): Likewise.
(legitimate_pic_address_disp_p): Likewise. (legitimate_pic_address_disp_p): Likewise.
...@@ -313,8 +323,9 @@ ...@@ -313,8 +323,9 @@
* mode-switching.c (optimize_mode_switching): Set correct RTL profile. * mode-switching.c (optimize_mode_switching): Set correct RTL profile.
* config/i386/i386.c (ix86_compute_frame_layout, * config/i386/i386.c (ix86_compute_frame_layout,
ix86_expand_epilogue, emit_i387_cw_initialization, ix86_expand_vector_move_misalign, ix86_expand_epilogue, emit_i387_cw_initialization,
ix86_fp_comparison_strategy, ix86_local_alignment): Fix use of size/speed predicates. ix86_expand_vector_move_misalign, ix86_fp_comparison_strategy,
ix86_local_alignment): Fix use of size/speed predicates.
2013-05-13 Jakub Jelinek <jakub@redhat.com> 2013-05-13 Jakub Jelinek <jakub@redhat.com>
...@@ -367,7 +378,7 @@ ...@@ -367,7 +378,7 @@
2013-05-13 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> 2013-05-13 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
* config/i386/i386.c (processor_target_table): Modified default * config/i386/i386.c (processor_target_table): Modified default
alignment values for AMD BD and BT architectures. alignment values for AMD BD and BT architectures.
2013-05-13 Marc Glisse <marc.glisse@inria.fr> 2013-05-13 Marc Glisse <marc.glisse@inria.fr>
......
gcc/config/i386/i386.c
...@@ -2892,9 +2892,10 @@ ix86_option_override_internal (bool main_args_p) ...@@ -2892,9 +2892,10 @@ ix86_option_override_internal (bool main_args_p)
{"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0}, {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
{"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX}, {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
{"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX}, {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
{"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW}, {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
{"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW}, {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
{"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE}, {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
PTA_MMX | PTA_SSE | PTA_FXSR},
{"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0}, {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
{"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0}, {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
{"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR}, {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
...@@ -2917,8 +2918,8 @@ ix86_option_override_internal (bool main_args_p) ...@@ -2917,8 +2918,8 @@ ix86_option_override_internal (bool main_args_p)
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_CX16 | PTA_FXSR}, | PTA_SSSE3 | PTA_CX16 | PTA_FXSR},
{"corei7", PROCESSOR_COREI7, CPU_COREI7, {"corei7", PROCESSOR_COREI7, CPU_COREI7,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_FXSR}, | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
{"corei7-avx", PROCESSOR_COREI7, CPU_COREI7, {"corei7-avx", PROCESSOR_COREI7, CPU_COREI7,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
...@@ -2940,49 +2941,49 @@ ix86_option_override_internal (bool main_args_p) ...@@ -2940,49 +2941,49 @@ ix86_option_override_internal (bool main_args_p)
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR}, | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
{"geode", PROCESSOR_GEODE, CPU_GEODE, {"geode", PROCESSOR_GEODE, CPU_GEODE,
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE}, PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
{"k6", PROCESSOR_K6, CPU_K6, PTA_MMX}, {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
{"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW}, {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
{"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW}, {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
{"athlon", PROCESSOR_ATHLON, CPU_ATHLON, {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE}, PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
{"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON, {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE}, PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
{"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON, {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE}, PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
{"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON, {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE}, PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_PRFCHW | PTA_FXSR},
{"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON, {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE}, PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_PRFCHW | PTA_FXSR},
{"x86-64", PROCESSOR_K8, CPU_K8, {"x86-64", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF}, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
{"k8", PROCESSOR_K8, CPU_K8, {"k8", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_NO_SAHF}, | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"k8-sse3", PROCESSOR_K8, CPU_K8, {"k8-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF}, | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"opteron", PROCESSOR_K8, CPU_K8, {"opteron", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_NO_SAHF}, | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"opteron-sse3", PROCESSOR_K8, CPU_K8, {"opteron-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF}, | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"athlon64", PROCESSOR_K8, CPU_K8, {"athlon64", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_NO_SAHF}, | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"athlon64-sse3", PROCESSOR_K8, CPU_K8, {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF}, | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"athlon-fx", PROCESSOR_K8, CPU_K8, {"athlon-fx", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_NO_SAHF}, | PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
{"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10, {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
| PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM}, | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
{"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10, {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
| PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM}, | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
{"bdver1", PROCESSOR_BDVER1, CPU_BDVER1, {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
...@@ -3592,14 +3593,18 @@ ix86_option_override_internal (bool main_args_p) ...@@ -3592,14 +3593,18 @@ ix86_option_override_internal (bool main_args_p)
ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit; ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
/* Enable SSE prefetch. */ /* Enable SSE prefetch. */
if (TARGET_SSE || TARGET_PRFCHW) if (TARGET_SSE || (TARGET_PRFCHW && !TARGET_3DNOW))
x86_prefetch_sse = true; x86_prefetch_sse = true;
/* Turn on popcnt instruction for -msse4.2 or -mabm. */ /* Enable prefetch{,w} instructions for -m3dnow. */
if (TARGET_3DNOW)
ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW & ~ix86_isa_flags_explicit;
/* Enable popcnt instruction for -msse4.2 or -mabm. */
if (TARGET_SSE4_2 || TARGET_ABM) if (TARGET_SSE4_2 || TARGET_ABM)
ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit; ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
/* Turn on lzcnt instruction for -mabm. */ /* Enable lzcnt instruction for -mabm. */
if (TARGET_ABM) if (TARGET_ABM)
ix86_isa_flags |= OPTION_MASK_ISA_LZCNT & ~ix86_isa_flags_explicit; ix86_isa_flags |= OPTION_MASK_ISA_LZCNT & ~ix86_isa_flags_explicit;
gcc/config/i386/i386.md
...@@ -17041,21 +17041,18 @@ ...@@ -17041,21 +17041,18 @@
[(prefetch (match_operand 0 "address_operand") [(prefetch (match_operand 0 "address_operand")
(match_operand:SI 1 "const_int_operand") (match_operand:SI 1 "const_int_operand")
(match_operand:SI 2 "const_int_operand"))] (match_operand:SI 2 "const_int_operand"))]
"TARGET_PREFETCH_SSE || TARGET_3DNOW" "TARGET_PREFETCH_SSE || TARGET_PRFCHW"
{ {
int rw = INTVAL (operands[1]); bool write = INTVAL (operands[1]) != 0;
int locality = INTVAL (operands[2]); int locality = INTVAL (operands[2]);
gcc_assert (rw == 0 || rw == 1);
gcc_assert (IN_RANGE (locality, 0, 3)); gcc_assert (IN_RANGE (locality, 0, 3));
if (TARGET_PRFCHW && rw)
operands[2] = GEN_INT (3);
/* Use 3dNOW prefetch in case we are asking for write prefetch not /* Use 3dNOW prefetch in case we are asking for write prefetch not
supported by SSE counterpart or the SSE prefetch is not available supported by SSE counterpart or the SSE prefetch is not available
(K6 machines). Otherwise use SSE prefetch as it allows specifying (K6 machines). Otherwise use SSE prefetch as it allows specifying
of locality. */ of locality. */
else if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw)) if (TARGET_PRFCHW && (write || !TARGET_PREFETCH_SSE))
operands[2] = GEN_INT (3); operands[2] = GEN_INT (3);
else else
operands[1] = const0_rtx; operands[1] = const0_rtx;
...@@ -17086,7 +17083,7 @@ ...@@ -17086,7 +17083,7 @@
[(prefetch (match_operand 0 "address_operand" "p") [(prefetch (match_operand 0 "address_operand" "p")
(match_operand:SI 1 "const_int_operand" "n") (match_operand:SI 1 "const_int_operand" "n")
(const_int 3))] (const_int 3))]
"TARGET_3DNOW || TARGET_PRFCHW" "TARGET_PRFCHW"
{ {
if (INTVAL (operands[1]) == 0) if (INTVAL (operands[1]) == 0)
return "prefetch\t%a0"; return "prefetch\t%a0";
......
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