[AArch64] Force __builtin_aarch64_fp[sc]r argument into a REG

The testcase triggered an ICE because the builtin expansion
code passed the output of expand_normal directly to the SET_FP[SC]R
generator, without forcing it into a register first.

gcc/
	* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin): Force
	__builtin_aarch64_fp[sc]r arguments into a register.

gcc/testsuite/
	* gcc.target/aarch64/fpcr_fpsr_1.c: New file.

From-SVN: r228116

gcc/ChangeLog

+2015-09-25  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin): Force
+	__builtin_aarch64_fp[sc]r arguments into a register.
+
 2015-09-25  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* config.gcc (x86_archs): Replace lakemount with lakemont.

gcc/config/aarch64/aarch64-builtins.c

@@ -1171,7 +1171,7 @@ aarch64_expand_builtin (tree exp,
 	  icode = (fcode == AARCH64_BUILTIN_SET_FPSR) ?
 	    CODE_FOR_set_fpsr : CODE_FOR_set_fpcr;
 	  arg0 = CALL_EXPR_ARG (exp, 0);
-	  op0 = expand_normal (arg0);
+	  op0 = force_reg (SImode, expand_normal (arg0));
 	  pat = GEN_FCN (icode) (op0);
 	}
       emit_insn (pat);

gcc/testsuite/ChangeLog

+2015-09-25  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/fpcr_fpsr_1.c: New file.
+
 2015-09-25  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gcc.target/i386/pr66749.c (dg-options): Replace

gcc/testsuite/gcc.target/aarch64/fpcr_fpsr_1.c

+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+f1 (int *x)
+{
+  __builtin_aarch64_set_fpsr (*x);
+}
+
+void
+f2 (int *x)
+{
+  __builtin_aarch64_set_fpcr (*x);
+}
+
+void
+f3 (int *x)
+{
+  *x = __builtin_aarch64_get_fpsr ();
+}
+
+void
+f4 (int *x)
+{
+  *x = __builtin_aarch64_get_fpcr ();
+}