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Commit e6c1be7e by Jakub Jelinek Committed by Jakub Jelinek
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sparc.md: Remove all traces of TARGET_LIVE_G0. 

	* config/sparc/sparc.md: Remove all traces of TARGET_LIVE_G0.
	(movsi_zero_liveg0): Remove.
	(movsf_insn_novis_liveg0): Remove.
	(negsi2): Remove.
	(negsi2_not_liveg0): Rename to negsi2.
	(one_cmplsi2): Remove.
	(one_cmplsi2_not_liveg0): Rename to one_cmplsi2.
	(one_cmplsi2_liveg0): Remove.
	* config/sparc/sparc.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE,
	MASK_LIVE_G0, MASK_BROKEN_SAVERESTORE): Remove.
	(CONDITIONAL_REGISTER_USAGE): Remove TARGET_LIVE_G0 if.
	(PREDICATE_CODES): Remove zero_operand.
	* config/sparc/sparc.c: Remove all traces of TARGET_LIVE_G0 and
	TARGET_BROKEN_SAVERESTORE.
	(zero_operand): Remove.
	* config/sparc/splet.h (SUBTARGET_SWITCHES): Remove -mlive-g0,
	-mno-live-g0, -mbroken-saverestore and -mno-broken-saverestore
	options.
	(SUBTARGET_OVERRIDE_OPTIONS): Remove.
	* config/sparc/linux-aout.h (TARGET_LIVE_G0,
	TARGET_BROKEN_SAVERESTORE): Remove.
	* config/sparc/linux.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE):
	Remove.
	* config/sparc/linux64.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE):
	Remove.
	* config/sparc/sol2.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE):
	Remove.

	* config/sparc/sparc.md (return_df_no_fpu): New pattern.

From-SVN: r32508
parent 0e091b52
Showing with 37 additions and 119 deletions
gcc/ChangeLog
2000-03-13 Jakub Jelinek <jakub@redhat.com>
* config/sparc/sparc.md: Remove all traces of TARGET_LIVE_G0.
(movsi_zero_liveg0): Remove.
(movsf_insn_novis_liveg0): Remove.
(negsi2): Remove.
(negsi2_not_liveg0): Rename to negsi2.
(one_cmplsi2): Remove.
(one_cmplsi2_not_liveg0): Rename to one_cmplsi2.
(one_cmplsi2_liveg0): Remove.
* config/sparc/sparc.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE,
MASK_LIVE_G0, MASK_BROKEN_SAVERESTORE): Remove.
(CONDITIONAL_REGISTER_USAGE): Remove TARGET_LIVE_G0 if.
(PREDICATE_CODES): Remove zero_operand.
* config/sparc/sparc.c: Remove all traces of TARGET_LIVE_G0 and
TARGET_BROKEN_SAVERESTORE.
(zero_operand): Remove.
* config/sparc/splet.h (SUBTARGET_SWITCHES): Remove -mlive-g0,
-mno-live-g0, -mbroken-saverestore and -mno-broken-saverestore
options.
(SUBTARGET_OVERRIDE_OPTIONS): Remove.
* config/sparc/linux-aout.h (TARGET_LIVE_G0,
TARGET_BROKEN_SAVERESTORE): Remove.
* config/sparc/linux.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE):
Remove.
* config/sparc/linux64.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE):
Remove.
* config/sparc/sol2.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE):
Remove.
* config/sparc/sparc.md (return_df_no_fpu): New pattern.
2000-03-13 Zack Weinberg <zack@wolery.cumb.org>
* cpplib.c (do_pragma_implementation): Fix off-by-one error
......
gcc/config/sparc/linux-aout.h
......@@ -102,12 +102,6 @@ Boston, MA 02111-1307, USA. */
#define ASM_SPEC \
"%{V} %{v:%{!V:-V}} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s %{fpic:-K PIC} %{fPIC:-K PIC}"
/* No weird SPARC variants on Linux */
#undef TARGET_LIVE_G0
#define TARGET_LIVE_G0 0
#undef TARGET_BROKEN_SAVERESTORE
#define TARGET_BROKEN_SAVERESTORE 0
/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
traps available which can get and set the condition codes
reliably. */
......
gcc/config/sparc/linux.h
......@@ -253,12 +253,6 @@ do { \
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
#endif
/* No weird SPARC variants on Linux */
#undef TARGET_LIVE_G0
#define TARGET_LIVE_G0 0
#undef TARGET_BROKEN_SAVERESTORE
#define TARGET_BROKEN_SAVERESTORE 0
/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
traps available which can get and set the condition codes
reliably. */
......
gcc/config/sparc/linux64.h
......@@ -378,12 +378,6 @@ do { \
/* #define DWARF_OFFSET_SIZE PTR_SIZE */
/* No weird SPARC variants on Linux */
#undef TARGET_LIVE_G0
#define TARGET_LIVE_G0 0
#undef TARGET_BROKEN_SAVERESTORE
#define TARGET_BROKEN_SAVERESTORE 0
#if TARGET_ARCH32
/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
traps available which can get and set the condition codes
......
gcc/config/sparc/sol2.h
......@@ -204,12 +204,6 @@ Boston, MA 02111-1307, USA. */
fixunsdfdi_libfunc \
= init_one_libfunc (TARGET_ARCH64 ? "__dtoul" : "__dtoull")
/* No weird SPARC variants on Solaris */
#undef TARGET_LIVE_G0
#define TARGET_LIVE_G0 0
#undef TARGET_BROKEN_SAVERESTORE
#define TARGET_BROKEN_SAVERESTORE 0
/* Solaris allows 64 bit out and global registers in 32 bit mode.
sparc_override_options will disable V8+ if not generating V9 code. */
#undef TARGET_DEFAULT
......
gcc/config/sparc/sparc.c
......@@ -377,8 +377,7 @@ v9_regcmp_p (code)
/* Operand constraints. */
/* Return non-zero only if OP is a register of mode MODE,
or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
%g0 may contain anything. */
or const0_rtx. */
int
reg_or_0_operand (op, mode)
......@@ -387,8 +386,6 @@ reg_or_0_operand (op, mode)
{
if (register_operand (op, mode))
return 1;
if (TARGET_LIVE_G0)
return 0;
if (op == const0_rtx)
return 1;
if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
......@@ -1132,16 +1129,6 @@ clobbered_register (op, mode)
return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
}
/* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns. */
int
zero_operand (op, mode)
rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
return op == const0_rtx;
}
/* Return 1 if OP is a valid operand for the source of a move insn. */
int
......@@ -2369,12 +2356,6 @@ eligible_for_epilogue_delay (trial, slot)
if (get_attr_length (trial) != 1)
return 0;
/* If %g0 is live, there are lots of things we can't handle.
Rather than trying to find them all now, let's punt and only
optimize things as necessary. */
if (TARGET_LIVE_G0)
return 0;
/* If there are any call-saved registers, we should scan TRIAL if it
does not reference them. For now just make it easy. */
if (num_gfregs)
......@@ -2391,11 +2372,6 @@ eligible_for_epilogue_delay (trial, slot)
return 0;
}
/* If only trivial `restore' insns work, nothing can go in the
delay slot. */
else if (TARGET_BROKEN_SAVERESTORE)
return 0;
pat = PATTERN (trial);
/* Otherwise, only operations which can be done in tandem with
......@@ -3342,7 +3318,7 @@ output_function_prologue (file, size, leaf_function)
if (actual_fsize == 0)
/* do nothing. */ ;
else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE)
else if (! leaf_function)
{
if (actual_fsize <= 4096)
fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
......@@ -3357,26 +3333,6 @@ output_function_prologue (file, size, leaf_function)
fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
}
}
else if (! leaf_function && TARGET_BROKEN_SAVERESTORE)
{
/* We assume the environment will properly handle or otherwise avoid
trouble associated with an interrupt occurring after the `save' or
trap occurring during it. */
fprintf (file, "\tsave\n");
if (actual_fsize <= 4096)
fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize);
else if (actual_fsize <= 8192)
{
fprintf (file, "\tadd\t%%fp, -4096, %%sp\n");
fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096);
}
else
{
build_big_number (file, -actual_fsize, "%g1");
fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n");
}
}
else /* leaf function */
{
if (actual_fsize <= 4096)
......@@ -5632,8 +5588,7 @@ print_operand (file, x, code)
{
fputc ('[', file);
/* Poor Sun assembler doesn't understand absolute addressing. */
if (CONSTANT_P (XEXP (x, 0))
&& ! TARGET_LIVE_G0)
if (CONSTANT_P (XEXP (x, 0)))
fputs ("%g0+", file);
output_address (XEXP (x, 0));
fputc (']', file);
......@@ -6660,12 +6615,6 @@ sparc_flat_eligible_for_epilogue_delay (trial, slot)
if (get_attr_length (trial) != 1)
return 0;
/* If %g0 is live, there are lots of things we can't handle.
Rather than trying to find them all now, let's punt and only
optimize things as necessary. */
if (TARGET_LIVE_G0)
return 0;
if (! reg_mentioned_p (stack_pointer_rtx, pat)
&& ! reg_mentioned_p (frame_pointer_rtx, pat))
return 1;
......
gcc/config/sparc/sparc.h
......@@ -522,20 +522,7 @@ extern int target_flags;
#define MASK_STACK_BIAS 0x80000
#define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
/* Non-zero means %g0 is a normal register.
We still clobber it as necessary, but we can't rely on it always having
a zero value.
We don't bother to support this in true 64 bit mode. */
#define MASK_LIVE_G0 0x100000
#define TARGET_LIVE_G0 (target_flags & MASK_LIVE_G0)
/* Non-zero means the cpu has broken `save' and `restore' insns, only
the trivial versions work (save %g0,%g0,%g0; restore %g0,%g0,%g0).
We assume the environment will properly handle or otherwise avoid
trouble associated with an interrupt occurring after the `save' or trap
occurring during it. */
#define MASK_BROKEN_SAVERESTORE 0x200000
#define TARGET_BROKEN_SAVERESTORE (target_flags & MASK_BROKEN_SAVERESTORE)
/* 0x100000,0x200000 unused */
/* Non-zero means -m{,no-}fpu was passed on the command line. */
#define MASK_FPU_SET 0x400000
......@@ -1042,8 +1029,6 @@ do \
fixed_regs[5] = 1; \
else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
fixed_regs[5] = 0; \
if (TARGET_LIVE_G0) \
fixed_regs[0] = 0; \
if (! TARGET_V9) \
{ \
int regno; \
......@@ -3370,7 +3355,6 @@ do { \
{"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
{"clobbered_register", {REG}}, \
{"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
{"zero_operand", {CONST_INT}}, \
{"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
{"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
......
gcc/config/sparc/splet.h
......@@ -21,20 +21,13 @@ Boston, MA 02111-1307, USA. */
#include "sparc/aout.h"
/* -mbroken-saverestore is not included here because the long term
default is -mno-broken-saverestore. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
/* -mlive-g0 is only supported on the sparclet. */
#undef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES \
{"big-endian", -MASK_LITTLE_ENDIAN, "Generate code for big endian" }, \
{"little-endian", MASK_LITTLE_ENDIAN, "Generate code for little endian" }, \
{"live-g0", MASK_LIVE_G0, "Use g0 as a normal register" }, \
{"no-live-g0", -MASK_LIVE_G0, "Register g0 is fixed with a zero value" }, \
{"broken-saverestore", MASK_BROKEN_SAVERESTORE, "Enable save/restore bug workarounds" }, \
{"no-broken-saverestore", -MASK_BROKEN_SAVERESTORE, "Disable save/restore bug workarouns" },
{"little-endian", MASK_LITTLE_ENDIAN, "Generate code for little endian" },
#undef ASM_SPEC
#define ASM_SPEC "%{mlittle-endian:-EL} %(asm_cpu)"
......@@ -51,19 +44,3 @@ Boston, MA 02111-1307, USA. */
#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
#undef WORDS_BIG_ENDIAN
#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
#undef SUBTARGET_OVERRIDE_OPTIONS
#define SUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_LIVE_G0) \
{ \
warning ("Option '-mlive-g0' deprecated."); \
target_flags &= ~MASK_LIVE_G0; \
} \
else if (TARGET_BROKEN_SAVERESTORE) \
{ \
warning ("Option '-mbroken-saverestore' deprecated."); \
target_flags &= ~MASK_BROKEN_SAVERESTORE; \
} \
} while (0)
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