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riscv-gcc-1
Commit e675f625 by David Edelsohn Committed by David Edelsohn
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rs6000.h (PREDICATE_CODES): Add CONSTANT_P_RTX. 

        * rs6000.h (PREDICATE_CODES): Add CONSTANT_P_RTX.
        * rs6000.md (movsi, movdi): Add CONSTANT_P_RTX.
        * rs6000.c (short_cint_operand): Add CONSTANT_P_RTX.
        (u_short_cint_operand): Same.
        (reg_or_cint_operand): Same.
        (logical_operand): Same.
        (input_operand): Same.
        (reg_or_short_operand): Use u_short_cint_operand.

From-SVN: r21323
parent 1ca2e73f
Showing with 42 additions and 23 deletions
gcc/ChangeLog
Tue Jul 21 15:49:31 1998 David Edelsohn <edelsohn@mhpcc.edu>
* rs6000.h (PREDICATE_CODES): Add CONSTANT_P_RTX.
* rs6000.md (movsi, movdi): Add CONSTANT_P_RTX.
* rs6000.c (short_cint_operand): Add CONSTANT_P_RTX.
(u_short_cint_operand): Same.
(reg_or_cint_operand): Same.
(logical_operand): Same.
(input_operand): Same.
(reg_or_short_operand): Use u_short_cint_operand.
Tue Jul 21 08:56:42 1998 Richard Henderson <rth@cygnus.com> Tue Jul 21 08:56:42 1998 Richard Henderson <rth@cygnus.com>
* alpha.md (fix_truncdfsi2, fix_truncsfsi2): Remove the define_expands, * alpha.md (fix_truncdfsi2, fix_truncsfsi2): Remove the define_expands,
......
gcc/config/rs6000/rs6000.c
...@@ -473,8 +473,9 @@ short_cint_operand (op, mode) ...@@ -473,8 +473,9 @@ short_cint_operand (op, mode)
register rtx op; register rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED; enum machine_mode mode ATTRIBUTE_UNUSED;
{ {
return (GET_CODE (op) == CONST_INT return ((GET_CODE (op) == CONST_INT
&& (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) < 0x10000); && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) < 0x10000)
|| GET_CODE (op) == CONSTANT_P_RTX);
} }
/* Similar for a unsigned D field. */ /* Similar for a unsigned D field. */
...@@ -484,8 +485,9 @@ u_short_cint_operand (op, mode) ...@@ -484,8 +485,9 @@ u_short_cint_operand (op, mode)
register rtx op; register rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED; enum machine_mode mode ATTRIBUTE_UNUSED;
{ {
return (GET_CODE (op) == CONST_INT return ((GET_CODE (op) == CONST_INT
&& (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0); && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0)
|| GET_CODE (op) == CONSTANT_P_RTX);
} }
/* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
...@@ -561,11 +563,7 @@ reg_or_u_short_operand (op, mode) ...@@ -561,11 +563,7 @@ reg_or_u_short_operand (op, mode)
register rtx op; register rtx op;
enum machine_mode mode; enum machine_mode mode;
{ {
if (GET_CODE (op) == CONST_INT return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
&& (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0)
return 1;
return gpc_reg_operand (op, mode);
} }
/* Return 1 is the operand is either a non-special register or ANY /* Return 1 is the operand is either a non-special register or ANY
...@@ -576,7 +574,9 @@ reg_or_cint_operand (op, mode) ...@@ -576,7 +574,9 @@ reg_or_cint_operand (op, mode)
register rtx op; register rtx op;
enum machine_mode mode; enum machine_mode mode;
{ {
return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode); return (GET_CODE (op) == CONST_INT
|| GET_CODE (op) == CONSTANT_P_RTX
|| gpc_reg_operand (op, mode));
} }
/* Return 1 if the operand is an operand that can be loaded via the GOT */ /* Return 1 if the operand is an operand that can be loaded via the GOT */
...@@ -860,7 +860,8 @@ logical_operand (op, mode) ...@@ -860,7 +860,8 @@ logical_operand (op, mode)
return (gpc_reg_operand (op, mode) return (gpc_reg_operand (op, mode)
|| (GET_CODE (op) == CONST_INT || (GET_CODE (op) == CONST_INT
&& ((INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0 && ((INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0
|| (INTVAL (op) & 0xffff) == 0))); || (INTVAL (op) & 0xffff) == 0))
|| GET_CODE (op) == CONSTANT_P_RTX);
} }
/* Return 1 if C is a constant that is not a logical operand (as /* Return 1 if C is a constant that is not a logical operand (as
...@@ -1094,7 +1095,9 @@ input_operand (op, mode) ...@@ -1094,7 +1095,9 @@ input_operand (op, mode)
/* Allow any integer constant. */ /* Allow any integer constant. */
if (GET_MODE_CLASS (mode) == MODE_INT if (GET_MODE_CLASS (mode) == MODE_INT
&& (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)) && (GET_CODE (op) == CONST_INT
|| GET_CODE (op) == CONSTANT_P_RTX
|| GET_CODE (op) == CONST_DOUBLE))
return 1; return 1;
/* For floating-point or multi-word mode, the only remaining valid type /* For floating-point or multi-word mode, the only remaining valid type
......
gcc/config/rs6000/rs6000.h
...@@ -3109,15 +3109,15 @@ do { \ ...@@ -3109,15 +3109,15 @@ do { \
/* Define the codes that are matched by predicates in rs6000.c. */ /* Define the codes that are matched by predicates in rs6000.c. */
#define PREDICATE_CODES \ #define PREDICATE_CODES \
{"short_cint_operand", {CONST_INT}}, \ {"short_cint_operand", {CONST_INT, CONSTANT_P_RTX}}, \
{"u_short_cint_operand", {CONST_INT}}, \ {"u_short_cint_operand", {CONST_INT, CONSTANT_P_RTX}}, \
{"non_short_cint_operand", {CONST_INT}}, \ {"non_short_cint_operand", {CONST_INT}}, \
{"gpc_reg_operand", {SUBREG, REG}}, \ {"gpc_reg_operand", {SUBREG, REG}}, \
{"cc_reg_operand", {SUBREG, REG}}, \ {"cc_reg_operand", {SUBREG, REG}}, \
{"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_short_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_cint_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
{"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \ {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
{"easy_fp_constant", {CONST_DOUBLE}}, \ {"easy_fp_constant", {CONST_DOUBLE}}, \
...@@ -3126,11 +3126,12 @@ do { \ ...@@ -3126,11 +3126,12 @@ do { \
{"volatile_mem_operand", {MEM}}, \ {"volatile_mem_operand", {MEM}}, \
{"offsettable_addr_operand", {REG, SUBREG, PLUS}}, \ {"offsettable_addr_operand", {REG, SUBREG, PLUS}}, \
{"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \ {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
{"add_operand", {SUBREG, REG, CONST_INT}}, \ {"add_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{"non_add_cint_operand", {CONST_INT}}, \ {"non_add_cint_operand", {CONST_INT}}, \
{"and_operand", {SUBREG, REG, CONST_INT}}, \ {"and_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ {"and64_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX, \
{"logical_operand", {SUBREG, REG, CONST_INT}}, \ CONST_DOUBLE}}, \
{"logical_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{"non_logical_cint_operand", {CONST_INT}}, \ {"non_logical_cint_operand", {CONST_INT}}, \
{"mask_operand", {CONST_INT}}, \ {"mask_operand", {CONST_INT}}, \
{"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \ {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \
...@@ -3138,7 +3139,8 @@ do { \ ...@@ -3138,7 +3139,8 @@ do { \
{"fpmem_operand", {REG}}, \ {"fpmem_operand", {REG}}, \
{"call_operand", {SYMBOL_REF, REG}}, \ {"call_operand", {SYMBOL_REF, REG}}, \
{"current_file_function_operand", {SYMBOL_REF}}, \ {"current_file_function_operand", {SYMBOL_REF}}, \
{"input_operand", {SUBREG, MEM, REG, CONST_INT, CONST_DOUBLE, SYMBOL_REF}}, \ {"input_operand", {SUBREG, MEM, REG, CONST_INT, CONSTANT_P_RTX, \
CONST_DOUBLE, SYMBOL_REF}}, \
{"load_multiple_operation", {PARALLEL}}, \ {"load_multiple_operation", {PARALLEL}}, \
{"store_multiple_operation", {PARALLEL}}, \ {"store_multiple_operation", {PARALLEL}}, \
{"branch_comparison_operator", {EQ, NE, LE, LT, GE, \ {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
......
gcc/config/rs6000/rs6000.md
...@@ -5415,7 +5415,8 @@ ...@@ -5415,7 +5415,8 @@
&& !flag_pic && !flag_pic
&& CONSTANT_P (operands[1]) && CONSTANT_P (operands[1])
&& GET_CODE (operands[1]) != HIGH && GET_CODE (operands[1]) != HIGH
&& GET_CODE (operands[1]) != CONST_INT) && GET_CODE (operands[1]) != CONST_INT
&& GET_CODE (operands[1]) != CONSTANT_P_RTX)
{ {
rtx target = (reload_completed || reload_in_progress) rtx target = (reload_completed || reload_in_progress)
? operands[0] : gen_reg_rtx (SImode); ? operands[0] : gen_reg_rtx (SImode);
...@@ -5469,6 +5470,7 @@ ...@@ -5469,6 +5470,7 @@
if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT) if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT)
&& CONSTANT_P (operands[1]) && CONSTANT_P (operands[1])
&& GET_CODE (operands[1]) != CONST_INT && GET_CODE (operands[1]) != CONST_INT
&& GET_CODE (operands[1]) != CONSTANT_P_RTX
&& GET_CODE (operands[1]) != HIGH && GET_CODE (operands[1]) != HIGH
&& ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
{ {
...@@ -6091,6 +6093,7 @@ ...@@ -6091,6 +6093,7 @@
&& CONSTANT_P (operands[1]) && CONSTANT_P (operands[1])
#if HOST_BITS_PER_WIDE_INT == 32 #if HOST_BITS_PER_WIDE_INT == 32
&& GET_CODE (operands[1]) != CONST_INT && GET_CODE (operands[1]) != CONST_INT
&& GET_CODE (operands[1]) != CONSTANT_P_RTX
#endif #endif
&& ! easy_fp_constant (operands[1], DImode) && ! easy_fp_constant (operands[1], DImode)
&& ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
......
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