[PR87815]Don't generate shift sequence for load replacement in DSE when the mode…

[PR87815]Don't generate shift sequence for load replacement in DSE when the mode size is not compile-time constant

The patch adds a check if the gap is compile-time constant.

This happens when dse decides to replace the load with previous store value.
The problem is that, shift sequence could not accept compile-time non-constant
mode operand.

gcc/

2018-11-12  Renlin Li  <renlin.li@arm.com>

	PR target/87815
	* dse.c (get_stored_val): Add check for compile-time
	constantness of gap.

gcc/testsuite/

2018-11-12  Renlin Li  <renlin.li@arm.com>

	PR target/87815
	* gcc.target/aarch64/sve/pr87815.c: New.

From-SVN: r266033

gcc/ChangeLog

+2018-11-12  Renlin Li  <renlin.li@arm.com>
+
+	PR target/87815
+	* dse.c (get_stored_val): Add check for compile-time constantness
+	of gap.
+
 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
 
 	* config/arm/arm-cpus.in (armv8_5, sb, predres): New features.

gcc/dse.c

@@ -1841,7 +1841,7 @@ get_stored_val (store_info *store_info, machine_mode read_mode,
   else
     gap = read_offset - store_info->offset;
 
-  if (maybe_ne (gap, 0))
+  if (gap.is_constant () && maybe_ne (gap, 0))
     {
       poly_int64 shift = gap * BITS_PER_UNIT;
       poly_int64 access_size = GET_MODE_SIZE (read_mode) + gap;

gcc/testsuite/ChangeLog

+2018-11-12  Renlin Li  <renlin.li@arm.com>
+
+	PR target/87815
+	* gcc.target/aarch64/sve/pr87815.c: New.
+
 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
 
 	* gcc.target/arm/multilib.exp: Add some -march=armv8.5-a

gcc/testsuite/gcc.target/aarch64/sve/pr87815.c

+/* { dg-do compile { target aarch64_asm_sve_ok } } */
+/* { dg-options "-O3" } */
+int a, b, d;
+short e;
+
+void f ()
+{
+  for (int i = 0; i < 8; i++)
+    {
+      e = b >= 2 ?: a >> b;
+      d = e && b;
+    }
+}