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Commit e61c94dd by Kirill Yukhin Committed by Kirill Yukhin
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Changelog entry: 

2012-07-25  Kirill Yukhin  <kirill.yukhin@intel.com>
            Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

        * common/config/i386/i386-common.c (OPTION_MASK_ISA_PRFCHW_SET): New.
        (OPTION_MASK_ISA_PRFCHW_UNSET): Likewise.
        (ix86_handle_option): Handle mprfchw option.
        * config.gcc (i[34567]86-*-*): Add prfchwintrin.h.
        (x86_64-*-*): Likewise.
        * config/i386/prfchwintrin.h: New header.
        * config/i386/cpuid.h (bit_PRFCHW): New.
        (bit_BMI): Formatting fix.
        (bit_HLE): Likewise.
        (bit_RTM): Likewise.
        * config/i386/driver-i386.c (host_detect_local_cpu): Detect
        PREFETCHW support.
        * config/i386/i386-c.c: Define __PRFCHW__ if needed.
        * config/i386/i386.c (ix86_target_string): Define
        -mprfchw option. Formatting fixes.
        (PTA_HLE): Formatting fix.
        (PTA_PRFCHW): New.
        (ix86_option_override_internal): Handle new option.
        (ix86_valid_target_attribute_inner_p): Add OPT_mprfchw.
        * config/i386/i386.h (TARGET_PRFCHW): New.
        * config/i386/i386.md (prefetch): Enable for TARGET_PRFCHW.
        * config/i386/i386.opt (mprfchw): New.
        * config/i386/mm3dnow.h: Move _m_prefetchw from here to
        prfchwintrin.h.
        * config/i386/x86intrin.h: Include prfchwintrin.h.

testsuite/Changelog entry:
2012-07-24  Kirill Yukhin  <kirill.yukhin@intel.com>
            Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

        * gcc.target/i386/prefetchw-1.c: New.
        * gcc.target/i386/sse-12.c: Add -mprfchw.
        * gcc.target/i386/sse-13.c: Ditto.
        * gcc.target/i386/sse-14.c: Ditto.
        * g++.dg/other/i386-2.C: Ditto.
        * g++.dg/other/i386-3.C: Ditto.




Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r189844
parent 4bd5abca
Showing with 164 additions and 32 deletions
gcc/ChangeLog
2012-07-25 Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* common/config/i386/i386-common.c (OPTION_MASK_ISA_PRFCHW_SET): New.
(OPTION_MASK_ISA_PRFCHW_UNSET): Likewise.
(ix86_handle_option): Handle mprfchw option.
* config.gcc (i[34567]86-*-*): Add prfchwintrin.h.
(x86_64-*-*): Likewise.
* config/i386/prfchwintrin.h: New header.
* config/i386/cpuid.h (bit_PRFCHW): New.
(bit_BMI): Formatting fix.
(bit_HLE): Likewise.
(bit_RTM): Likewise.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect
PREFETCHW support.
* config/i386/i386-c.c: Define __PRFCHW__ if needed.
* config/i386/i386.c (ix86_target_string): Define
-mprfchw option. Formatting fixes.
(PTA_HLE): Formatting fix.
(PTA_PRFCHW): New.
(ix86_option_override_internal): Handle new option.
(ix86_valid_target_attribute_inner_p): Add OPT_mprfchw.
* config/i386/i386.h (TARGET_PRFCHW): New.
* config/i386/i386.md (prefetch): Enable for TARGET_PRFCHW.
* config/i386/i386.opt (mprfchw): New.
* config/i386/mm3dnow.h: Move _m_prefetchw from here to
prfchwintrin.h.
* config/i386/x86intrin.h: Include prfchwintrin.h.
2012-07-25 Sergey Melnikov <sergey.melnikov@intel.com>
* config/i386/i386.md (stack_protect_set): Disable the pattern
......
gcc/common/config/i386/i386-common.c
......@@ -55,6 +55,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA_AVX2_SET \
(OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
......@@ -123,6 +124,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
#define OPTION_MASK_ISA_AVX2_UNSET OPTION_MASK_ISA_AVX2
#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
......@@ -568,6 +570,19 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
case OPT_mprfchw:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
}
return true;
/* Comes from final.c -- no real reason to change it. */
#define MAX_CODE_ALIGN 16
......
gcc/config.gcc
......@@ -361,7 +361,7 @@ i[34567]86-*-*)
ia32intrin.h cross-stdarg.h lwpintrin.h popcntintrin.h
lzcntintrin.h bmiintrin.h bmi2intrin.h tbmintrin.h
avx2intrin.h fmaintrin.h f16cintrin.h rtmintrin.h
xtestintrin.h"
xtestintrin.h prfchwintrin.h"
;;
x86_64-*-*)
cpu_type=i386
......@@ -375,7 +375,7 @@ x86_64-*-*)
ia32intrin.h cross-stdarg.h lwpintrin.h popcntintrin.h
lzcntintrin.h bmiintrin.h tbmintrin.h bmi2intrin.h
avx2intrin.h fmaintrin.h f16cintrin.h rtmintrin.h
xtestintrin.h"
xtestintrin.h prfchwintrin.h"
need_64bit_hwint=yes
;;
ia64-*-*)
......
gcc/config/i386/cpuid.h
......@@ -65,11 +65,14 @@
/* Extended Features (%eax == 7) */
#define bit_FSGSBASE (1 << 0)
#define bit_BMI (1 << 3)
#define bit_HLE (1 << 4)
#define bit_BMI (1 << 3)
#define bit_HLE (1 << 4)
#define bit_AVX2 (1 << 5)
#define bit_BMI2 (1 << 8)
#define bit_RTM (1 << 11)
#define bit_PRFCHW (1 << 8)
#define bit_RTM (1 << 11)
#define bit_RDSEED (1 << 18)
#define bit_ADX (1 << 19)
#if defined(__i386__) && defined(__PIC__)
/* %ebx may be the PIC register. */
......
gcc/config/i386/driver-i386.c
......@@ -399,6 +399,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
unsigned int has_hle = 0, has_rtm = 0;
unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
unsigned int has_prfchw = 0;
bool arch;
......@@ -465,6 +466,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
has_avx2 = ebx & bit_AVX2;
has_bmi2 = ebx & bit_BMI2;
has_fsgsbase = ebx & bit_FSGSBASE;
has_prfchw = ecx & bit_PRFCHW;
}
/* Check cpuid level of extended features. */
......@@ -745,11 +747,12 @@ const char *host_detect_local_cpu (int argc, const char **argv)
const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
options = concat (options, cx16, sahf, movbe, ase, pclmul,
popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
hle, rdrnd, f16c, fsgsbase, NULL);
hle, rdrnd, f16c, fsgsbase, prfchw, NULL);
}
done:
......
gcc/config/i386/i386-c.c
......@@ -296,6 +296,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__RDRND__");
if (isa_flag & OPTION_MASK_ISA_F16C)
def_or_undef (parse_in, "__F16C__");
if (isa_flag & OPTION_MASK_ISA_PRFCHW)
def_or_undef (parse_in, "__PRFCHW__");
if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE))
def_or_undef (parse_in, "__SSE_MATH__");
if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE2))
......
gcc/config/i386/i386.c
......@@ -2748,7 +2748,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
preceding options while match those first. */
static struct ix86_target_opts isa_opts[] =
{
{ "-mfma4", OPTION_MASK_ISA_FMA4 },
{ "-mfma4", OPTION_MASK_ISA_FMA4 },
{ "-mfma", OPTION_MASK_ISA_FMA },
{ "-mxop", OPTION_MASK_ISA_XOP },
{ "-mlwp", OPTION_MASK_ISA_LWP },
......@@ -2756,17 +2756,18 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
{ "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
{ "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
{ "-mssse3", OPTION_MASK_ISA_SSSE3 },
{ "-msse3", OPTION_MASK_ISA_SSE3 },
{ "-msse2", OPTION_MASK_ISA_SSE2 },
{ "-msse3", OPTION_MASK_ISA_SSE3 },
{ "-msse2", OPTION_MASK_ISA_SSE2 },
{ "-msse", OPTION_MASK_ISA_SSE },
{ "-m3dnow", OPTION_MASK_ISA_3DNOW },
{ "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
{ "-mmmx", OPTION_MASK_ISA_MMX },
{ "-mabm", OPTION_MASK_ISA_ABM },
{ "-mbmi", OPTION_MASK_ISA_BMI },
{ "-mbmi2", OPTION_MASK_ISA_BMI2 },
{ "-mbmi2", OPTION_MASK_ISA_BMI2 },
{ "-mlzcnt", OPTION_MASK_ISA_LZCNT },
{ "-mhle", OPTION_MASK_ISA_HLE },
{ "-mprfchw", OPTION_MASK_ISA_PRFCHW },
{ "-mtbm", OPTION_MASK_ISA_TBM },
{ "-mpopcnt", OPTION_MASK_ISA_POPCNT },
{ "-mmovbe", OPTION_MASK_ISA_MOVBE },
......@@ -2775,7 +2776,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
{ "-mpclmul", OPTION_MASK_ISA_PCLMUL },
{ "-mfsgsbase", OPTION_MASK_ISA_FSGSBASE },
{ "-mrdrnd", OPTION_MASK_ISA_RDRND },
{ "-mf16c", OPTION_MASK_ISA_F16C },
{ "-mf16c", OPTION_MASK_ISA_F16C },
{ "-mrtm", OPTION_MASK_ISA_RTM },
};
......@@ -3042,7 +3043,8 @@ ix86_option_override_internal (bool main_args_p)
#define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
#define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
#define PTA_RTM (HOST_WIDE_INT_1 << 32)
#define PTA_HLE (HOST_WIDE_INT_1 << 33)
#define PTA_HLE (HOST_WIDE_INT_1 << 33)
#define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
/* if this reaches 64, need to widen struct pta flags below */
static struct pta
......@@ -3528,6 +3530,9 @@ ix86_option_override_internal (bool main_args_p)
if (processor_alias_table[i].flags & PTA_HLE
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_HLE))
ix86_isa_flags |= OPTION_MASK_ISA_HLE;
if (processor_alias_table[i].flags & PTA_PRFCHW
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PRFCHW))
ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW;
if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
x86_prefetch_sse = true;
......@@ -3735,10 +3740,11 @@ ix86_option_override_internal (bool main_args_p)
/* Turn on MMX builtins for -msse. */
if (TARGET_SSE)
{
ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
x86_prefetch_sse = true;
}
ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
/* Enable SSE prefetch. */
if (TARGET_SSE || TARGET_PRFCHW)
x86_prefetch_sse = true;
/* Turn on popcnt instruction for -msse4.2 or -mabm. */
if (TARGET_SSE4_2 || TARGET_ABM)
......@@ -4348,6 +4354,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
IX86_ATTR_ISA ("f16c", OPT_mf16c),
IX86_ATTR_ISA ("rtm", OPT_mrtm),
IX86_ATTR_ISA ("hle", OPT_mhle),
IX86_ATTR_ISA ("prfchw", OPT_mprfchw),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
gcc/config/i386/i386.h
......@@ -76,6 +76,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define TARGET_F16C OPTION_ISA_F16C
#define TARGET_RTM OPTION_ISA_RTM
#define TARGET_HLE OPTION_ISA_HLE
#define TARGET_PRFCHW OPTION_ISA_PRFCHW
#define TARGET_LP64 OPTION_ABI_64
#define TARGET_X32 OPTION_ABI_X32
......
gcc/config/i386/i386.md
......@@ -17626,12 +17626,14 @@
gcc_assert (locality >= 0 && locality <= 3);
gcc_assert (GET_MODE (operands[0]) == Pmode
|| GET_MODE (operands[0]) == VOIDmode);
if (TARGET_PRFCHW && rw)
operands[2] = GEN_INT (3);
/* Use 3dNOW prefetch in case we are asking for write prefetch not
supported by SSE counterpart or the SSE prefetch is not available
(K6 machines). Otherwise use SSE prefetch as it allows specifying
of locality. */
if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
else if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
operands[2] = GEN_INT (3);
else
operands[1] = const0_rtx;
......@@ -17662,7 +17664,7 @@
[(prefetch (match_operand:P 0 "address_operand" "p")
(match_operand:SI 1 "const_int_operand" "n")
(const_int 3))]
"TARGET_3DNOW"
"TARGET_3DNOW || TARGET_PRFCHW"
{
if (INTVAL (operands[1]) == 0)
return "prefetch\t%a0";
......
gcc/config/i386/i386.opt
......@@ -532,6 +532,10 @@ mhle
Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save
Support Hardware Lock Elision prefixes
mprfchw
Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save
Support PREFETCHW instruction
mtbm
Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
Support TBM built-in functions and code generation
......
gcc/config/i386/mm3dnow.h
......@@ -30,6 +30,7 @@
#ifdef __3dNOW__
#include <mmintrin.h>
#include <prfchwintrin.h>
extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_m_femms (void)
......@@ -157,12 +158,6 @@ _m_prefetch (void *__P)
__builtin_prefetch (__P, 0, 3 /* _MM_HINT_T0 */);
}
extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_m_prefetchw (void *__P)
{
__builtin_prefetch (__P, 1, 3 /* _MM_HINT_T0 */);
}
extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_m_from_float (float __A)
{
......
gcc/config/i386/prfchwintrin.h 0 → 100644
/* Copyright (C) 2012 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#if !defined _X86INTRIN_H_INCLUDED && !defined _MM3DNOW_H_INCLUDED
# error "Never use <prfchwintrin.h> directly; include <x86intrin.h> or <mm3dnow.h> instead."
#endif
#if !defined (__PRFCHW__) && !defined (__3dNOW__)
# error "PRFCHW instruction not enabled"
#endif /* __PRFCHW__ or __3dNOW__*/
#ifndef _PRFCHWINTRIN_H_INCLUDED
#define _PRFCHWINTRIN_H_INCLUDED
extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_m_prefetchw (void *__P)
{
__builtin_prefetch (__P, 1, 3 /* _MM_HINT_T0 */);
}
#endif /* _PRFCHWINTRIN_H_INCLUDED */
gcc/config/i386/x86intrin.h
......@@ -97,4 +97,8 @@
#include <popcntintrin.h>
#endif
#ifdef __PRFCHW__
#include <prfchwintrin.h>
#endif
#endif /* _X86INTRIN_H_INCLUDED */
gcc/testsuite/ChangeLog
2012-07-25 Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* gcc.target/i386/prefetchw-1.c: New.
* gcc.target/i386/sse-12.c: Add -mprfchw.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* g++.dg/other/i386-2.C: Ditto.
* g++.dg/other/i386-3.C: Ditto.
2012-07-24 Janis Johnson <janisjo@codesourcery.com>
* lib/gcc-dg.exp (process-message): Don't ignore errors.
......
gcc/testsuite/g++.dg/other/i386-2.C
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
......
gcc/testsuite/g++.dg/other/i386-3.C
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
......
gcc/testsuite/gcc.target/i386/prefetchw-1.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-mprfchw -O2" } */
/* { dg-final { scan-assembler "\[ \\t\]+prefetchw\[ \\t\]+" } } */
#include <x86intrin.h>
void *p;
void extern
prefetchw__test (void)
{
_m_prefetchw (p);
}
gcc/testsuite/gcc.target/i386/sse-12.c
......@@ -3,7 +3,7 @@
popcntintrin.h and mm_malloc.h are usable
with -O -std=c89 -pedantic-errors. */
/* { dg-do compile } */
/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
#include <x86intrin.h>
......
gcc/testsuite/gcc.target/i386/sse-13.c
/* { dg-do compile } */
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
#include <mm_malloc.h>
......
gcc/testsuite/gcc.target/i386/sse-14.c
/* { dg-do compile } */
/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm" } */
/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
#include <mm_malloc.h>
......
gcc/testsuite/gcc.target/i386/sse-22.c
......@@ -50,7 +50,7 @@
#ifndef DIFFERENT_PRAGMAS
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm")
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,prfchw")
#endif
/* Following intrinsics require immediate arguments. They
......@@ -264,7 +264,7 @@ test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1)
/* x86intrin.h (FMA4/XOP/LWP/BMI/BMI2/TBM/LZCNT/FMA). */
#ifdef DIFFERENT_PRAGMAS
#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma")
#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,prfchw")
#endif
#include <x86intrin.h>
/* xopintrin.h */
......
gcc/testsuite/gcc.target/i386/sse-23.c
......@@ -183,7 +183,7 @@
/* rtmintrin.h */
#define __builtin_ia32_xabort(M) __builtin_ia32_xabort(1)
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm")
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,prfchw")
#include <wmmintrin.h>
#include <smmintrin.h>
#include <mm3dnow.h>
......
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