ia64.c (predicate_operator): New.

        * config/ia64/ia64.c (predicate_operator): New.
        (ia64_print_operand): Handle 'J'.
        (rtx_needs_barrier): Handle COND_EXEC.
        * config/ia64/ia64.h (BRANCH_COST): Define.
        (PREDICATE_CODES): Update.
        * config/ia64/ia64.md: Docuement used unspec values.
        (attr predicable): New.
        (movxf, movxf_internal): New.
        (extendsfdf2): Don't comment out nop.
        (floatdidf2): Remove.
        (truncxfsf2, truncxfdf2, floatdixf2): New.
        (abssi2, absdi2): Put the neg in the "true" slot.
        (conditional branch instructions): Mark not predicable.
        (cmov*_internal): Use predicate_operator.  Split to cond_exec.
        (abs*_internal): Likewise.
        (alloc, set_bsp): Mark not predicable.
        (barrier, insn_group_barrier, flush_cache): Likewise.
        (define_cond_exec): New.

From-SVN: r33754

gcc/ChangeLog

 2000-05-06  Richard Henderson  <rth@cygnus.com>
 
+	* config/ia64/ia64.c (predicate_operator): New.
+	(ia64_print_operand): Handle 'J'.
+	(rtx_needs_barrier): Handle COND_EXEC.
+	* config/ia64/ia64.h (BRANCH_COST): Define.
+	(PREDICATE_CODES): Update.
+	* config/ia64/ia64.md: Docuement used unspec values.
+	(attr predicable): New.
+	(movxf, movxf_internal): New.
+	(extendsfdf2): Don't comment out nop.
+	(floatdidf2): Remove.
+	(truncxfsf2, truncxfdf2, floatdixf2): New.
+	(abssi2, absdi2): Put the neg in the "true" slot.
+	(conditional branch instructions): Mark not predicable.
+	(cmov*_internal): Use predicate_operator.  Split to cond_exec.
+	(abs*_internal): Likewise.
+	(alloc, set_bsp): Mark not predicable.
+	(barrier, insn_group_barrier, flush_cache): Likewise.
+	(define_cond_exec): New.
+
+2000-05-06  Richard Henderson  <rth@cygnus.com>
+
 	* c-decl.c: Include "tm_p.h".
 
 	* config/ia64/ia64-protos.h: Rearrange decls to reduce ifdef madness.

gcc/config/ia64/ia64.c

@@ -468,6 +468,17 @@ call_multiple_values_operation (op, mode)
   return 1;
 }
 
+/* Return 1 if this operator is valid for predication.  */
+
+int
+predicate_operator (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  enum rtx_code code = GET_CODE (op);
+  return ((GET_MODE (op) == mode || mode == VOIDmode)
+	  && (code == EQ || code == NE));
+}
 
 /* Structure to be filled in by ia64_compute_frame_size with register
    save masks and offsets for the current function.  */
@@ -1683,6 +1694,7 @@ ia64_print_operand_address (stream, address)
    F	A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
         a floating point register emitted normally.
    I	Invert a predicate register by adding 1.
+   J    Select the proper predicate register for a condition.
    O	Append .acq for volatile load.
    P	Postincrement of a MEM.
    Q	Append .rel for volatile store.
@@ -1742,6 +1754,10 @@ ia64_print_operand (file, x, code)
       fputs (reg_names [REGNO (x) + 1], file);
       return;
 
+    case 'J':
+      fputs (reg_names [REGNO (XEXP (x, 0)) + (GET_CODE (x) == EQ)], file);
+      return;
+
     case 'O':
       if (MEM_VOLATILE_P (x))
 	fputs(".acq", file);
@@ -2382,6 +2398,27 @@ rtx_needs_barrier (x, flags, pred)
 	}
       break;
 
+    case COND_EXEC:
+      /* X is a predicated instruction.  */
+
+      cond = COND_EXEC_TEST (x);
+      if (pred)
+	abort ();
+      need_barrier = rtx_needs_barrier (cond, flags, 0);
+
+      if (GET_CODE (cond) == EQ)
+	is_complemented = 1;
+      cond = XEXP (cond, 0);
+      if (GET_CODE (cond) != REG
+	  && REGNO_REG_CLASS (REGNO (cond)) != PR_REGS)
+	abort ();
+      pred = REGNO (cond);
+      if (is_complemented)
+	++pred;
+
+      need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
+      return need_barrier;
+
     case CLOBBER:
 #if 0
     case USE:

gcc/config/ia64/ia64.h

@@ -1922,9 +1922,13 @@ do {									\
 /* #define MEMORY_MOVE_COST(M,C,I) */
 
 /* A C expression for the cost of a branch instruction.  A value of 1 is the
-   default; other values are interpreted relative to that.  */
-/* ??? Investigate.  Might get better code by defining this.  */
-/* #define BRANCH_COST */
+   default; other values are interpreted relative to that.  Used by the 
+   if-conversion code as max instruction count.  */
+/* ??? This requires investigation.  The primary effect might be how
+   many additional insn groups we run into, vs how good the dynamic
+   branch predictor is.  */
+
+#define BRANCH_COST 6
 
 /* Define this macro as a C expression which is nonzero if accessing less than
    a word of memory (i.e. a `char' or a `short') is no faster than accessing a
@@ -2726,7 +2730,8 @@ do {									\
 { "reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE, CONSTANT_P_RTX}},	\
 { "normal_comparison_operator", {EQ, NE, GT, LE, GTU, LEU}},		\
 { "adjusted_comparison_operator", {LT, GE, LTU, GEU}},			\
-{ "call_multiple_values_operation", {PARALLEL}},
+{ "call_multiple_values_operation", {PARALLEL}},			\
+{ "predicate_operator", {NE, EQ}},
 
 /* An alias for a machine mode name.  This is the machine mode that elements of
    a jump-table should have.  */