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riscv-gcc-1
Commit e5837c07 by Kazu Hirata Committed by Kazu Hirata
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alias.c: Fix comment formatting. 

	* alias.c: Fix comment formatting.
	* recog.c: Likewise.
	* config/cris/cris.c: Likewise.
	* config/cris/cris.h: Likewise.
	* config/i960/i960.c: Likewise.
	* config/i960/i960.h: Likewise.

From-SVN: r46640
parent bc70506b
Showing with 60 additions and 51 deletions
gcc/ChangeLog
2001-10-30 Kazu Hirata <kazu@hxi.com>
* alias.c: Fix comment formatting.
* recog.c: Likewise.
* config/cris/cris.c: Likewise.
* config/cris/cris.h: Likewise.
* config/i960/i960.c: Likewise.
* config/i960/i960.h: Likewise.
2001-10-30 Kazu Hirata <kazu@hxi.com>
* config/arm/arm.c: Fix a comment typo.
* config/arm/arm.h: Likewise.
* config/ia64/ia64.c: Likewise.
......
gcc/alias.c
......@@ -510,7 +510,7 @@ get_alias_set (t)
if (decl && DECL_POINTER_ALIAS_SET_KNOWN_P (decl))
{
/* If we haven't computed the actual alias set, do it now. */
/* If we haven't computed the actual alias set, do it now. */
if (DECL_POINTER_ALIAS_SET (decl) == -2)
{
/* No two restricted pointers can point at the same thing.
......
gcc/config/cris/cris.c
......@@ -665,7 +665,7 @@ cris_target_asm_function_prologue (file, size)
cfa_write_offset -= size;
/* Get a contiguous sequence of registers, starting with r0, that need
to be saved. */
to be saved. */
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
{
if ((((regs_ever_live[regno]
......@@ -774,7 +774,7 @@ cris_target_asm_function_prologue (file, size)
else
{
/* Avoid printing multiple subsequent sub:s for sp. FIXME:
Clean up the conditional expression. */
Clean up the conditional expression. */
fprintf (file, "\tsub%s %d,$sp\n",
ADDITIVE_SIZE_MODIFIER ((last_movem_reg + 1) * 4 + size),
(last_movem_reg + 1) * 4 + size);
......@@ -849,7 +849,7 @@ saved_regs_mentioned (x)
const char *fmt;
RTX_CODE code;
/* Mainly stolen from refers_to_regno_p in rtlanal.c. */
/* Mainly stolen from refers_to_regno_p in rtlanal.c. */
code = GET_CODE (x);
......@@ -1166,7 +1166,7 @@ cris_target_asm_function_epilogue (file, size)
them. */
if (pretend)
{
/* Since srp is stored on the way, we need to restore it first. */
/* Since srp is stored on the way, we need to restore it first. */
if (return_address_on_stack)
{
if (*save_last && file)
......@@ -1184,7 +1184,7 @@ cris_target_asm_function_epilogue (file, size)
ADDITIVE_SIZE_MODIFIER (pretend), pretend);
}
/* Here's where we have a delay-slot we need to fill. */
/* Here's where we have a delay-slot we need to fill. */
if (file && current_function_epilogue_delay_list)
{
/* If gcc has allocated an insn for the epilogue delay slot, but
......@@ -1442,7 +1442,7 @@ cris_print_operand (file, x, code)
return;
case 0:
/* No code, print as usual. */
/* No code, print as usual. */
break;
default:
......@@ -1454,7 +1454,7 @@ cris_print_operand (file, x, code)
}
}
/* Print an operand as without a modifier letter. */
/* Print an operand as without a modifier letter. */
switch (GET_CODE (operand))
{
case REG:
......@@ -1675,7 +1675,7 @@ cris_initial_elimination_offset (fromreg, toreg)
&& toreg == STACK_POINTER_REGNUM)
return fp_sp_offset;
/* We need to balance out the frame pointer here. */
/* We need to balance out the frame pointer here. */
if (fromreg == ARG_POINTER_REGNUM
&& toreg == STACK_POINTER_REGNUM)
return ap_fp_offset + fp_sp_offset - 4;
......@@ -1779,13 +1779,13 @@ cris_notice_update_cc (exp, insn)
return;
/* Record CC0 changes, so we do not have to output multiple
test insns. */
test insns. */
if (SET_DEST (exp) == cc0_rtx)
{
cc_status.value1 = SET_SRC (exp);
cc_status.value2 = 0;
/* Handle flags for the special btstq on one bit. */
/* Handle flags for the special btstq on one bit. */
if (GET_CODE (SET_SRC (exp)) == ZERO_EXTRACT
&& XEXP (SET_SRC (exp), 1) == const1_rtx)
{
......@@ -1805,7 +1805,7 @@ cris_notice_update_cc (exp, insn)
&& XEXP (SET_SRC (exp), 1) != const0_rtx)
/* For some reason gcc will not canonicalize compare
operations, reversing the sign by itself if
operands are in wrong order. */
operands are in wrong order. */
/* (But NOT inverted; eq is still eq.) */
cc_status.flags = CC_REVERSED;
......@@ -1823,14 +1823,14 @@ cris_notice_update_cc (exp, insn)
&& REG_P (XEXP (SET_DEST (exp), 0))))
{
/* A register is set; normally CC is set to show that no
test insn is needed. Catch the exceptions. */
test insn is needed. Catch the exceptions. */
/* If not to cc0, then no "set"s in non-natural mode give
ok cc0... */
if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD
|| GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT)
{
/* ... except add:s and sub:s in DImode. */
/* ... except add:s and sub:s in DImode. */
if (GET_MODE (SET_DEST (exp)) == DImode
&& (GET_CODE (SET_SRC (exp)) == PLUS
|| GET_CODE (SET_SRC (exp)) == MINUS))
......
gcc/config/cris/cris.h
......@@ -264,7 +264,7 @@ extern int target_flags;
/* If to use condition-codes generated by insns other than the
immediately preceding compare/test insn.
Used to check for errors in notice_update_cc. */
Used to check for errors in notice_update_cc. */
#define TARGET_MASK_CCINIT 2
#define TARGET_CCINIT (target_flags & TARGET_MASK_CCINIT)
......@@ -519,11 +519,11 @@ extern int target_flags;
#define FUNCTION_BOUNDARY 16
/* Do not change BIGGEST_ALIGNMENT (when optimizing), as it will affect
strange places, at least in 2.1. */
strange places, at least in 2.1. */
#define BIGGEST_ALIGNMENT 8
/* If -m16bit, -m16-bit, -malign or -mdata-align,
align everything to 16 bit. */
align everything to 16 bit. */
#define DATA_ALIGNMENT(TYPE, BASIC_ALIGN) \
(TARGET_DATA_ALIGN \
? (TARGET_ALIGN_BY_32 \
......@@ -735,7 +735,7 @@ enum reg_class {NO_REGS, ALL_REGS, LIM_REG_CLASSES};
0)
/* It is really simple to make up a 0.0; it is the same as int-0 in
IEEE754. */
IEEE754. */
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'G' && ((VALUE) == CONST0_RTX (DFmode) \
|| (VALUE) == CONST0_RTX (SFmode)))
......@@ -873,7 +873,7 @@ enum reg_class {NO_REGS, ALL_REGS, LIM_REG_CLASSES};
#define STACK_POINTER_REGNUM 14
/* Register used for frame pointer. This is also the last of the saved
registers, when a frame pointer is not used. */
registers, when a frame pointer is not used. */
#define FRAME_POINTER_REGNUM 8
/* Faked register, is always eliminated. We need it to eliminate
......@@ -1078,7 +1078,7 @@ struct cum_args {int regs;};
Anyway, trampolines are rare enough that we can cope with this
somewhat lack of elegance.
(Do not be tempted to "straighten up" whitespace in the asms; the
assembler #NO_APP state mandates strict spacing). */
assembler #NO_APP state mandates strict spacing). */
#define TRAMPOLINE_TEMPLATE(FILE) \
do \
{ \
......@@ -1099,7 +1099,7 @@ struct cum_args {int regs;};
/* CRIS wants instructions on word-boundary.
Note that due to a bug (reported) in 2.7.2 and earlier, this is
actually treated as alignment in _bytes_, not _bits_. (Obviously
this is not fatal, only a slight waste of stack space). */
this is not fatal, only a slight waste of stack space). */
#define TRAMPOLINE_ALIGNMENT 16
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
......@@ -1296,7 +1296,7 @@ struct cum_args {int regs;};
\
if (REGNO (XEXP (X, 1)) >= FIRST_PSEUDO_REGISTER) \
{ \
/* Second reg is pseudo, reload it. */ \
/* Second reg is pseudo, reload it. */ \
push_reload (XEXP (X, 1), NULL_RTX, &XEXP (X, 1), \
NULL, \
GENERAL_REGS, GET_MODE (X), VOIDmode, 0, 0, \
......@@ -1308,7 +1308,7 @@ struct cum_args {int regs;};
&& (REGNO (XEXP (XEXP (X, 0), 0)) \
>= FIRST_PSEUDO_REGISTER)) \
{ \
/* First one is a pseudo - reload that. */ \
/* First one is a pseudo - reload that. */ \
push_reload (XEXP (XEXP (X, 0), 0), NULL_RTX, \
&XEXP (XEXP (X, 0), 0), NULL, \
GENERAL_REGS, \
......@@ -1543,7 +1543,7 @@ struct cum_args {int regs;};
while (0)
/* This is what is used by gcc for 64-bit floats,
not the "long double" one. */
not the "long double" one. */
#define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
ASM_OUTPUT_LONG_DOUBLE (FILE, VALUE)
......@@ -1585,7 +1585,7 @@ struct cum_args {int regs;};
#define IS_ASM_LOGICAL_LINE_SEPARATOR(C) (C) == '@'
/* FIXME: These are undocumented. */
/* FIXME: These are undocumented. */
/* We need to define these, since the 2byte, 4byte, 8byte op:s are only
available in ELF. These "normal" pseudos do not have any alignment
constraints or side-effects. */
......@@ -1812,7 +1812,7 @@ struct cum_args {int regs;};
/* Node: DBX Options */
/* Is this correct? Check later. */
/* Is this correct? Check later. */
#define DBX_NO_XREFS
#define DBX_CONTIN_LENGTH 0
......
gcc/config/i960/i960.c
......@@ -507,7 +507,7 @@ i960_address_cost (x)
Return 1 if we have written out everything that needs to be done to
do the move. Otherwise, return 0 and the caller will emit the move
normally. */
normally. */
int
emit_move_sequence (operands, mode)
......@@ -520,7 +520,7 @@ emit_move_sequence (operands, mode)
&& (operands[1] != const0_rtx || current_function_args_size
|| current_function_varargs || current_function_stdarg
|| rtx_equal_function_value_matters))
/* Here we use the same test as movsi+1 pattern -- see i960.md. */
/* Here we use the same test as movsi+1 pattern -- see i960.md. */
operands[1] = force_reg (mode, operands[1]);
/* Storing multi-word values in unaligned hard registers to memory may
......@@ -1031,7 +1031,7 @@ i960_function_name_declare (file, name, fndecl)
leaf_proc_ok = 0;
}
/* See if caller passes in an address to return value. */
/* See if caller passes in an address to return value. */
if (aggregate_value_p (DECL_RESULT (fndecl)))
{
......@@ -1173,7 +1173,7 @@ compute_frame_size (size)
}
/* Here register group is range of registers which can be moved by
one i960 instruction. */
one i960 instruction. */
struct reg_group
{
......@@ -1189,7 +1189,7 @@ static void i960_arg_size_and_align PARAMS ((enum machine_mode, tree, int *, int
/* The following functions forms the biggest as possible register
groups with registers in STATE. REGS contain states of the
registers in range [start, finish_reg). The function returns the
number of groups formed. */
number of groups formed. */
static int
i960_form_reg_groups (start_reg, finish_reg, regs, state, reg_groups)
int start_reg;
......@@ -1223,7 +1223,7 @@ i960_form_reg_groups (start_reg, finish_reg, regs, state, reg_groups)
return nw;
}
/* We sort register winodws in descending order by length. */
/* We sort register winodws in descending order by length. */
static int
i960_reg_group_compare (group1, group2)
const void *group1;
......@@ -1242,7 +1242,7 @@ i960_reg_group_compare (group1, group2)
/* Split the first register group in REG_GROUPS on subgroups one of
which will contain SUBGROUP_LENGTH registers. The function
returns new number of winodws. */
returns new number of winodws. */
static int
i960_split_reg_group (reg_groups, nw, subgroup_length)
struct reg_group *reg_groups;
......@@ -1253,11 +1253,11 @@ i960_split_reg_group (reg_groups, nw, subgroup_length)
/* This guarantees correct alignments of the two subgroups for
i960 (see spliting for the group length 2, 3, 4). More
generalized algorithm would require splitting the group more
two subgroups. */
two subgroups. */
subgroup_length = reg_groups->length - subgroup_length;
/* More generalized algorithm would require to try merging
subgroups here. But in case i960 it always results in failure
because of register group alignment. */
because of register group alignment. */
reg_groups[nw].length = reg_groups->length - subgroup_length;
reg_groups[nw].start_reg = reg_groups->start_reg + subgroup_length;
nw++;
......@@ -1284,9 +1284,9 @@ i960_output_function_prologue (file, size)
/* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
somewhere. */
int regs[FIRST_PSEUDO_REGISTER];
/* All global registers (which must be saved) divided by groups. */
/* All global registers (which must be saved) divided by groups. */
struct reg_group global_reg_groups [16];
/* All local registers (which are available) divided by groups. */
/* All local registers (which are available) divided by groups. */
struct reg_group local_reg_groups [16];
......@@ -2132,7 +2132,7 @@ legitimize_address (x, oldx, mode)
#if 0
/* Return the most stringent alignment that we are willing to consider
objects of size SIZE and known alignment ALIGN as having. */
objects of size SIZE and known alignment ALIGN as having. */
int
i960_alignment (size, align)
......@@ -2244,7 +2244,7 @@ i960_expr_alignment (x, size)
case SYMBOL_REF:
/* If this is a valid program, objects are guaranteed to be
correctly aligned for whatever size the reference actually is. */
correctly aligned for whatever size the reference actually is. */
align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
break;
......@@ -2556,7 +2556,7 @@ i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
If there are no stack arguments but there are exactly NPARM_REGS
registers, either there were no extra arguments or the caller
allocated an argument block. */
allocated an argument block. */
if (cum->ca_nstackparms == 0 && first_reg < NPARM_REGS && !no_rtl)
{
......
gcc/config/i960/i960.h
......@@ -100,7 +100,7 @@ Boston, MA 02111-1307, USA. */
that -O means FP elimination. Addressing through sp requires
negative offset and more one word addressing in the most cases
(offsets except for 0-4095 require one more word). Therefore we've
not defined the macro. */
not defined the macro. */
/*#define CAN_DEBUG_WITHOUT_FP*/
/* Do leaf procedure and tail call optimizations for -O2 and higher. */
......@@ -154,7 +154,7 @@ extern int i960_last_maxbitalignment;
/* The following three are mainly used to provide a little sanity checking
against the -mARCH flags given. The Jx series, for the purposes of
gcc, is a Kx with a data cache. */
gcc, is a Kx with a data cache. */
/* Nonzero if we should generate code for the KA and similar processors.
No FPU, no microcode instructions. */
......@@ -422,7 +422,7 @@ extern int target_flags;
#define POINTER_SIZE 32
/* Width in bits of a long double. Define to 96, and let
ROUND_TYPE_ALIGN adjust the alignment for speed. */
ROUND_TYPE_ALIGN adjust the alignment for speed. */
#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 96)
/* ??? This must be a constant, because real.c and real.h test it with #if. */
......@@ -634,7 +634,7 @@ extern int target_flags;
This is an array of structures. Each structure initializes one pair
of eliminable registers. The "from" register number is given first,
followed by "to". Eliminations of the same "from" register are listed
in order of preference.. */
in order of preference.. */
#define ELIMINABLE_REGS {{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
......@@ -1118,7 +1118,7 @@ struct cum_args { int ca_nregparms; int ca_nstackparms; };
In each case, scale can be 1, 2, 4, 8, or 16. */
/* Returns 1 if the scale factor of an index term is valid. */
/* Returns 1 if the scale factor of an index term is valid. */
#define SCALE_TERM_P(X) \
(GET_CODE (X) == CONST_INT \
&& (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \
......@@ -1167,7 +1167,7 @@ struct cum_args { int ca_nregparms; int ca_nstackparms; };
/* Define as C expression which evaluates to nonzero if the tablejump
instruction expects the table to contain offsets from the address of the
table.
Do not define this if the table should contain absolute addresses. */
Do not define this if the table should contain absolute addresses. */
/* #define CASE_VECTOR_PC_RELATIVE 1 */
/* Specify the tree operation to be used to convert reals to integers. */
......@@ -1198,7 +1198,7 @@ struct cum_args { int ca_nregparms; int ca_nstackparms; };
/* Nonzero if access to memory by bytes is no faster than for words.
Value changed to 1 after reports of poor bitfield code with g++.
Indications are that code is usually as good, sometimes better. */
Indications are that code is usually as good, sometimes better. */
#define SLOW_BYTE_ACCESS 1
......@@ -1213,7 +1213,7 @@ struct cum_args { int ca_nregparms; int ca_nstackparms; };
#define STORE_FLAG_VALUE 1
/* Define this to be nonzero if shift instructions ignore all but the low-order
few bits. */
few bits. */
#define SHIFT_COUNT_TRUNCATED 0
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
......@@ -1345,7 +1345,7 @@ extern struct rtx_def *i960_compare_op0, *i960_compare_op1;
#define DBX_CONTIN_LENGTH 1500
/* This is how to output a note to DBX telling it the line number
to which the following sequence of instructions corresponds. */
to which the following sequence of instructions corresponds. */
#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \
{ if (write_symbols == SDB_DEBUG) { \
......@@ -1370,7 +1370,7 @@ extern struct rtx_def *i960_compare_op0, *i960_compare_op1;
assemble_name (FILE, NAME); \
fputs ("\n", FILE); }
/* The prefix to add to user-visible assembler symbols. */
/* The prefix to add to user-visible assembler symbols. */
#define USER_LABEL_PREFIX "_"
......
gcc/recog.c
......@@ -3121,7 +3121,7 @@ peephole2_optimize (dump_file)
XEXP (note, 0),
REG_NOTES (new_insn));
default:
/* Discard all other reg notes. */
/* Discard all other reg notes. */
break;
}
......
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