ia64.c (emit_insn_group_barriers): Special case epilogue_deallocate_stack.

        * config/ia64/ia64.c (emit_insn_group_barriers): Special case
        epilogue_deallocate_stack.

        * config/ia64/ia64.c (ia64_print_operand) [case D]: Emit
        completers for UNORDERED and ORDERED as well.
        * config/ia64/ia64.md (bunordered, bordered): New.
        (sunordered, sordered): New.

From-SVN: r34734

gcc/ChangeLog

+2000-06-27  Richard Henderson  <rth@cygnus.com>
+
+	* config/ia64/ia64.c (emit_insn_group_barriers): Special case
+	epilogue_deallocate_stack.
+
+	* config/ia64/ia64.c (ia64_print_operand) [case D]: Emit
+	completers for UNORDERED and ORDERED as well.
+	* config/ia64/ia64.md (bunordered, bordered): New.
+	(sunordered, sordered): New.
+
 Tue Jun 27 12:14:12 MET DST 2000  Jan Hubicka  <jh@suse.cz>
 
 	* genattrtab.c (write_attr_value): Do not abort for CONST_INT operands.

gcc/config/ia64/ia64.c

@@ -1777,6 +1777,8 @@ ia64_print_operand (file, x, code)
      rtx    x;
      int    code;
 {
+  const char *str;
+
   switch (code)
     {
     case 0:
@@ -1796,7 +1798,22 @@ ia64_print_operand (file, x, code)
       }
 
     case 'D':
-      fputs (GET_CODE (x) == NE ? "neq" : GET_RTX_NAME (GET_CODE (x)), file);
+      switch (GET_CODE (x))
+	{
+	case NE:
+	  str = "neq";
+	  break;
+	case UNORDERED:
+	  str = "unord";
+	  break;
+	case ORDERED:
+	  str = "ord";
+	  break;
+	default:
+	  str = GET_RTX_NAME (GET_CODE (x));
+	  break;
+	}
+      fputs (str, file);
       return;
 
     case 'E':
@@ -1805,13 +1822,14 @@ ia64_print_operand (file, x, code)
 
     case 'F':
       if (x == CONST0_RTX (GET_MODE (x)))
-	fputs (reg_names [FR_REG (0)], file);
+	str = reg_names [FR_REG (0)];
       else if (x == CONST1_RTX (GET_MODE (x)))
-	fputs (reg_names [FR_REG (1)], file);
+	str = reg_names [FR_REG (1)];
       else if (GET_CODE (x) == REG)
-	fputs (reg_names [REGNO (x)], file);
+	str = reg_names [REGNO (x)];
       else
 	abort ();
+      fputs (str, file);
       return;
 
     case 'I':
@@ -2834,8 +2852,15 @@ emit_insn_group_barriers (insns)
 	    break;
 	  else
 	    {
+	      rtx pat = PATTERN (insn);
+
+	      /* We play dependency tricks with the epilogue in order to
+		 get proper schedules.  Undo this for dv analysis.  */
+	      if (INSN_CODE (insn) == CODE_FOR_epilogue_deallocate_stack)
+		pat = XVECEXP (pat, 0, 0);
+
 	      memset (rws_insn, 0, sizeof (rws_insn));
-	      need_barrier |= rtx_needs_barrier (PATTERN (insn), flags, 0);
+	      need_barrier |= rtx_needs_barrier (pat, flags, 0);
 
 	      /* Check to see if the previous instruction was a volatile
 		 asm.  */

gcc/config/ia64/ia64.md

@@ -2153,6 +2153,40 @@
   operands[3] = ia64_compare_op1;
 }")
 
+(define_expand "bunordered"
+  [(set (match_dup 1)
+	(unordered:CC (match_dup 2)
+		      (match_dup 3)))
+   (set (pc)
+	(if_then_else (ne:CC (match_dup 1)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (CCmode);
+  operands[2] = ia64_compare_op0;
+  operands[3] = ia64_compare_op1;
+}")
+
+(define_expand "bordered"
+  [(set (match_dup 1)
+	(ordered:CC (match_dup 2)
+		      (match_dup 3)))
+   (set (pc)
+	(if_then_else (ne:CC (match_dup 1)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (CCmode);
+  operands[2] = ia64_compare_op0;
+  operands[3] = ia64_compare_op1;
+}")
+
 (define_insn "*br_true"
   [(set (pc)
 	(if_then_else (match_operator 0 "predicate_operator"
@@ -2323,6 +2357,34 @@
   operands[3] = ia64_compare_op1;
 }")
 
+(define_expand "sunordered"
+  [(set (match_dup 1)
+	(unordered:CC (match_dup 2)
+		      (match_dup 3)))
+   (set (match_operand:DI 0 "register_operand" "")
+	(ne:DI (match_dup 1) (const_int 0)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (CCmode);
+  operands[2] = ia64_compare_op0;
+  operands[3] = ia64_compare_op1;
+}")
+
+(define_expand "sordered"
+  [(set (match_dup 1)
+	(ordered:CC (match_dup 2)
+		      (match_dup 3)))
+   (set (match_operand:DI 0 "register_operand" "")
+	(ne:DI (match_dup 1) (const_int 0)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (CCmode);
+  operands[2] = ia64_compare_op0;
+  operands[3] = ia64_compare_op1;
+}")
+
 ;; Don't allow memory as destination here, because cmov/cmov/st is more
 ;; efficient than mov/mov/cst/cst.