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lvzhengyang
riscv-gcc-1
Commits
e52e05ca
Commit
e52e05ca
authored
Mar 29, 1995
by
Michael Meissner
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Do not move float values through memory to get to/from gp registers if -msoft-float.
From-SVN: r9242
parent
515f0e72
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gcc/config/rs6000/rs6000.md
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gcc/config/rs6000/rs6000.md
View file @
e52e05ca
...
@@ -3901,11 +3901,11 @@
...
@@ -3901,11 +3901,11 @@
[
(set_attr "type" "
*,*
,
*,compare,*
,
*,load,*
")
[
(set_attr "type" "
*,*
,
*,compare,*
,
*,load,*
")
(set_attr "length" "
*,*
,12,
*,8,*
,
*,*
")])
(set_attr "length" "
*,*
,12,
*,8,*
,
*,*
")])
;; For floating-point, we normally deal with the floating-point registers
.
;; For floating-point, we normally deal with the floating-point registers
;;
The sole exception is that parameter passing can produce floating-point
;;
unless -msoft-float is used. The sole exception is that parameter passing
;;
values in fixed-point registers. Unless the value is a simple constant
;;
can produce floating-point values in fixed-point registers. Unless the
;;
or already in memory, we deal with this by allocating memory and copying
;;
value is a simple constant or already in memory, we deal with this by
;; the value explicitly via that memory location.
;;
allocating memory and copying
the value explicitly via that memory location.
(define_expand "movsf"
(define_expand "movsf"
[
(set (match_operand:SF 0 "nonimmediate_operand" "")
[
(set (match_operand:SF 0 "nonimmediate_operand" "")
(match_operand:SF 1 "any_operand" ""))]
(match_operand:SF 1 "any_operand" ""))]
...
@@ -3923,70 +3923,73 @@
...
@@ -3923,70 +3923,73 @@
&& REGNO (SUBREG_REG (operands
[
1
]
)) < FIRST_PSEUDO_REGISTER)
&& REGNO (SUBREG_REG (operands
[
1
]
)) < FIRST_PSEUDO_REGISTER)
operands
[
1
]
= alter_subreg (operands
[
1
]
);
operands
[
1
]
= alter_subreg (operands
[
1
]
);
if (
GET_CODE (operands
[
1
]
) == REG && REGNO (operands
[
1
]
) < 32
)
if (
TARGET_HARD_FLOAT
)
{
{
/
*
If this is a store to memory or another integer register do the
if (GET_CODE (operands
[
1
]
) == REG && REGNO (operands
[
1
]
) < 32)
move directly. Otherwise store to a temporary stack slot and
load from there into a floating point register.
*
/
if (GET_CODE (operands[0]) == MEM
|| (GET_CODE (operands[0]) == REG
&& (REGNO (operands[0]) < 32
|| (reload_in_progress
&& REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
{
{
emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
/
*
If this is a store to memory or another integer register do the
operand_subword (operands[1], 0, 0, SFmode));
move directly. Otherwise store to a temporary stack slot and
DONE;
load from there into a floating point register.
*
/
}
else
if (GET_CODE (operands[0]) == MEM
{
|| (GET_CODE (operands[0]) == REG
rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
&& (REGNO (operands[0]) < 32
|| (reload_in_progress
emit_move_insn (stack_slot, operands[1]);
&& REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
emit_move_insn (operands[0], stack_slot);
{
DONE;
emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
operand_subword (operands[1], 0, 0, SFmode));
DONE;
}
else
{
rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
emit_move_insn (stack_slot, operands[1]);
emit_move_insn (operands[0], stack_slot);
DONE;
}
}
}
}
if (GET_CODE (operands
[
0
]
) == MEM)
if (GET_CODE (operands[0]) == MEM)
{
/
*
If operands
[
1
]
is a register, it may have double-precision data
in it, so truncate it to single precision. We need not do
this for POWERPC.
*
/
if (! TARGET_POWERPC && TARGET_HARD_FLOAT && GET_CODE (operands
[
1
]
) == REG)
{
{
rtx newreg = reload_in_progress ? operands
[
1
]
: gen_reg_rtx (SFmode);
/* If operands[1] is a register, it may have double-precision data
emit_insn (gen_truncdfsf2 (newreg,
in it, so truncate it to single precision. We need not do
gen_rtx (SUBREG, DFmode, operands
[
1
]
, 0)));
this for POWERPC. */
operands
[
1
]
= newreg;
if (! TARGET_POWERPC && TARGET_HARD_FLOAT && GET_CODE (operands[1]) == REG)
{
rtx newreg = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
emit_insn (gen_truncdfsf2 (newreg,
gen_rtx (SUBREG, DFmode, operands[1], 0)));
operands[1] = newreg;
}
operands[1] = force_reg (SFmode, operands[1]);
}
}
operands[1] = force_reg (SFmode, operands[1]);
if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
}
{
if (GET_CODE (operands[1]) == MEM
if (GET_CODE (operands
[
0
]
) == REG && REGNO (operands
[
0
]
) < 32)
{
if (GET_CODE (operands
[
1
]
) == MEM
#if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
#if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
|| GET_CODE (operands
[
1
]
) == CONST_DOUBLE
|| GET_CODE (operands
[
1
]
) == CONST_DOUBLE
#endif
#endif
|| (GET_CODE (operands
[
1
]
) == REG
|| (GET_CODE (operands
[
1
]
) == REG
&& (REGNO (operands
[
1
]
) < 32
&& (REGNO (operands
[
1
]
) < 32
|| (reload_in_progress
|| (reload_in_progress
&& REGNO (operands
[
1
]
) >= FIRST_PSEUDO_REGISTER))))
&& REGNO (operands
[
1
]
) >= FIRST_PSEUDO_REGISTER))))
{
{
emit_move_insn (operand_subword (operands
[
0
]
, 0, 0, SFmode),
emit_move_insn (operand_subword (operands
[
0
]
, 0, 0, SFmode),
operand_subword (operands
[
1
]
, 0, 0, SFmode));
operand_subword (operands
[
1
]
, 0, 0, SFmode));
DONE;
DONE;
}
}
else
else
{
{
rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
emit_move_insn (stack_slot, operands[1]);
emit_move_insn (stack_slot, operands[1]);
emit_move_insn (operands[0], stack_slot);
emit_move_insn (operands[0], stack_slot);
DONE;
DONE;
}
}
}
}
}
...
...
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