builtins-3.c: Remove ISA 3.0 word variant builtin test cases for vec_mule, and vec_mulo.

gcc/testsuite/ChangeLog:

2017-08-04  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/builtins-3.c: Remove ISA 3.0 word variant
	builtin test cases for vec_mule, and vec_mulo.
	* gcc.target/powerpc/builtins-3-p8.c: Add  ISA 3.0 word variant
	builtin test cases for vec_mule, and vec_mulo.

From-SVN: r250876

gcc/testsuite/ChangeLog

+2017-08-04  Carl Love  <cel@us.ibm.com>
+
+	* gcc.target/powerpc/builtins-3.c: Remove ISA 3.0 word variant
+	builtin test cases for vec_mule, and vec_mulo.
+	* gcc.target/powerpc/builtins-3-p8.c: Add ISA 3.0 word variant
+	builtin test cases for vec_mule, and vec_mulo.
+
 2017-08-04  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR target/81590

gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c

@@ -85,6 +85,30 @@ test_vss_mradds_vss_vss (vector signed short x, vector signed short y,
 	return vec_mradds (x, y, z);
 }
 
+vector signed long long
+test_vsll_mule_vsi_vsi (vector signed int x, vector signed int y)
+{
+	return vec_mule (x, y);
+}
+
+vector unsigned long long
+test_vull_mule_vui_vui (vector unsigned int x, vector unsigned int y)
+{
+	return vec_mule (x, y);
+}
+
+vector signed long long
+test_vsll_mulo_vsi_vsi (vector signed int x, vector signed int y)
+{
+	return vec_mulo (x, y);
+}
+
+vector unsigned long long
+test_vull_mulo_vui_vui (vector unsigned int x, vector unsigned int y)
+{
+	return vec_mulo (x, y);
+}
+
 /* Expected test results:
 
      test_eq_long_long                         1 vcmpequd inst
@@ -98,7 +122,12 @@ test_vss_mradds_vss_vss (vector signed short x, vector signed short y,
      test_unsigned_int_popcnt_signed_int       2 vpopcntw
      test_unsigned_int_popcnt_unsigned_int     1 vpopcntd
      test_unsigned_long_long_popcnt_unsigned_long 1 vpopcntd
-     test_vss_mradds_vss_vsss                  1 vmhraddshs */
+     test_vss_mradds_vss_vsss                  1 vmhraddshs
+     test_vsll_mulo_vsi_vsi                    1 vmulosw
+     test_vull_mulo_vui_vui                    1 vmulouw
+     test_vsll_mule_vsi_vsi                    1 vmulesw
+     test_vull_mule_vui_vui                    1 vmuleuw
+ */
 
 /* { dg-final { scan-assembler-times "vcmpequd" 1 } } */
 /* { dg-final { scan-assembler-times "vpkudum"  1 } } */
@@ -109,3 +138,7 @@ test_vss_mradds_vss_vss (vector signed short x, vector signed short y,
 /* { dg-final { scan-assembler-times "vpopcntw" 2 } } */
 /* { dg-final { scan-assembler-times "vpopcntd" 2 } } */
 /* { dg-final { scan-assembler-times "vmhraddshs"  1 } } */
+/* { dg-final { scan-assembler-times "vmulosw"  1 } } */
+/* { dg-final { scan-assembler-times "vmulouw"  1 } } */
+/* { dg-final { scan-assembler-times "vmulesw"  1 } } */
+/* { dg-final { scan-assembler-times "vmuleuw"  1 } } */

gcc/testsuite/gcc.target/powerpc/builtins-3.c

@@ -112,30 +112,6 @@ test_vull_slo_vull_vuc (vector unsigned long long x, vector unsigned char y)
 	return vec_slo (x, y);
 }
 
-vector signed long long
-test_vsll_mule_vsi_vsi (vector signed int x, vector signed int y)
-{
-	return vec_mule (x, y);
-}
-
-vector unsigned long long
-test_vull_mule_vui_vui (vector unsigned int x, vector unsigned int y)
-{
-	return vec_mule (x, y);
-}
-
-vector signed long long
-test_vsll_mulo_vsi_vsi (vector signed int x, vector signed int y)
-{
-	return vec_mulo (x, y);
-}
-
-vector unsigned long long
-test_vull_mulo_vui_vui (vector unsigned int x, vector unsigned int y)
-{
-	return vec_mulo (x, y);
-}
-
 vector signed char
 test_vsc_sldw_vsc_vsc (vector signed char x, vector signed char y)
 {
@@ -207,10 +183,6 @@ test_vul_sldw_vul_vul (vector unsigned long long x,
      test_vsll_slo_vsll_vuc    1 vslo
      test_vull_slo_vsll_vsc    1 vslo
      test_vull_slo_vsll_vuc    1 vslo
-     test_vsll_mulo_vsi_vsi    1 vmulosw
-     test_vull_mulo_vui_vui    1 vmulouw
-     test_vsll_mule_vsi_vsi    1 vmulesw
-     test_vull_mule_vui_vui    1 vmuleuw
      test_vsc_mulo_vsc_vsc     1 xxsldwi
      test_vuc_mulo_vuc_vuc     1 xxsldwi
      test_vssi_mulo_vssi_vssi  1 xxsldwi
@@ -236,8 +208,4 @@ test_vul_sldw_vul_vul (vector unsigned long long x,
 /* { dg-final { scan-assembler-times "xvnegsp"  1 } } */
 /* { dg-final { scan-assembler-times "xvnegdp"  1 } } */
 /* { dg-final { scan-assembler-times "vslo"     4 } } */
-/* { dg-final { scan-assembler-times "vmulosw"  1 } } */
-/* { dg-final { scan-assembler-times "vmulouw"  1 } } */
-/* { dg-final { scan-assembler-times "vmulesw"  1 } } */
-/* { dg-final { scan-assembler-times "vmuleuw"  1 } } */
 /* { dg-final { scan-assembler-times "xxsldwi"  8 } } */