i960.c (i960_output_move_double_zero, [...]): New functions for moving zeros.

1999-01-14  Vladimir N. Makarov  <vmakarov@cygnus.com>
	* config/i960/i960.c (i960_output_move_double_zero,
	i960_output_move_quad_zero): New functions for moving zeros.
	(i960_output_move_double, i960_output_move_quad): Additional code
	for situation when moving unaligned register group.
        * config/i960/i960.h (i960_output_move_double_zero,
	i960_output_move_quad_zero): The function definitions.
	* config/i960/i960.md (movdi+1, movti+1): Usage of the functions.

From-SVN: r24666

gcc/ChangeLog

+1999-01-14  Vladimir N. Makarov  <vmakarov@cygnus.com>
+
+	* config/i960/i960.c (i960_output_move_double_zero,
+	i960_output_move_quad_zero): New functions for moving zeros.
+	(i960_output_move_double, i960_output_move_quad): Additional code
+	for situation when moving unaligned register group.
+	
+        * config/i960/i960.h (i960_output_move_double_zero,
+	i960_output_move_quad_zero): The function definitions.
+
+	* config/i960/i960.md (movdi+1, movti+1): Usage of the functions.
+
 1999-01-13  Vladimir N. Makarov  <vmakarov@cygnus.com>
 
 	* config/i960/i960.c (i960_function_prologue): New code (optimal

gcc/config/i960/i960.c

@@ -575,7 +575,7 @@ i960_address_cost (x)
 
    Return 1 if we have written out everything that needs to be done to
    do the move.  Otherwise, return 0 and the caller will emit the move
-   normally.  */
+   normally. */
 
 int
 emit_move_sequence (operands, mode)
@@ -583,8 +583,12 @@ emit_move_sequence (operands, mode)
      enum machine_mode mode;
 {
   /* We can only store registers to memory.  */
-
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG)
+  
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG
+      && (operands[1] != const0_rtx || current_function_args_size
+	  || current_function_varargs || current_function_stdarg
+	  || rtx_equal_function_value_matters))
+    /* Here we use the same test as movsi+1 pattern -- see i960.md. */
     operands[1] = force_reg (mode, operands[1]);
 
   /* Storing multi-word values in unaligned hard registers to memory may
@@ -673,8 +677,13 @@ i960_output_move_double (dst, src)
     {
       if (REGNO (src) & 1)
 	{
-	  /* This is handled by emit_move_sequence so we shouldn't get here.  */
-	  abort ();
+	  operands[0] = dst;
+	  operands[1] = adj_offsettable_operand (dst, UNITS_PER_WORD);
+	  if (! memory_address_p (word_mode, XEXP (operands[1], 0)))
+	    abort ();
+	  operands[2] = src;
+	  output_asm_insn ("st	%2,%0\n\tst	%D2,%1", operands);
+	  return "";
 	}
       return "stl	%1,%0";
     }
@@ -682,6 +691,22 @@ i960_output_move_double (dst, src)
     abort ();
 }
 
+/* Output assembler to move a double word zero.  */
+
+char *
+i960_output_move_double_zero (dst)
+     rtx dst;
+{
+  rtx operands[2];
+
+  operands[0] = dst;
+    {
+      operands[1] = adj_offsettable_operand (dst, 4);
+      output_asm_insn ("st	g14,%0\n\tst	g14,%1", operands);
+    }
+  return "";
+}
+
 /* Output assembler to move a quad word value.  */
 
 char *
@@ -744,14 +769,40 @@ i960_output_move_quad (dst, src)
     {
       if (REGNO (src) & 3)
 	{
-	  /* This is handled by emit_move_sequence so we shouldn't get here.  */
-	  abort ();
+	  operands[0] = dst;
+	  operands[1] = adj_offsettable_operand (dst, UNITS_PER_WORD);
+	  operands[2] = adj_offsettable_operand (dst, 2*UNITS_PER_WORD);
+	  operands[3] = adj_offsettable_operand (dst, 3*UNITS_PER_WORD);
+	  if (! memory_address_p (word_mode, XEXP (operands[3], 0)))
+	    abort ();
+	  operands[4] = src;
+	  output_asm_insn ("st	%4,%0\n\tst	%D4,%1\n\tst	%E4,%2\n\tst	%F4,%3", operands);
+	  return "";
 	}
       return "stq	%1,%0";
     }
   else
     abort ();
 }
+
+/* Output assembler to move a quad word zero.  */
+
+char *
+i960_output_move_quad_zero (dst)
+     rtx dst;
+{
+  rtx operands[4];
+
+  operands[0] = dst;
+    {
+      operands[1] = adj_offsettable_operand (dst, 4);
+      operands[2] = adj_offsettable_operand (dst, 8);
+      operands[3] = adj_offsettable_operand (dst, 12);
+      output_asm_insn ("st	g14,%0\n\tst	g14,%1\n\tst	g14,%2\n\tst	g14,%3", operands);
+    }
+  return "";
+}
+
 
 /* Emit insns to load a constant to non-floating point registers.
    Uses several strategies to try to use as few insns as possible.  */

gcc/config/i960/i960.h

@@ -1564,7 +1564,9 @@ extern char *i960_output_ldconst ();
 extern char *i960_output_call_insn ();
 extern char *i960_output_ret_insn ();
 extern char *i960_output_move_double ();
+extern char *i960_output_move_double_zero ();
 extern char *i960_output_move_quad ();
+extern char *i960_output_move_quad_zero ();
 
 /* Defined in reload.c, and used in insn-recog.c.  */
 

gcc/config/i960/i960.md

@@ -835,8 +835,7 @@
     case 2:
       return i960_output_ldconst (operands[0], operands[1]);
     case 5:
-      operands[1] = adj_offsettable_operand (operands[0], 4);
-      return \"st	g14,%0\;st	g14,%1\";
+       return i960_output_move_double_zero (operands[0]);
     }
 }"
   [(set_attr "type" "move,move,load,load,store,store")])
@@ -915,10 +914,7 @@
     case 2:
       return i960_output_ldconst (operands[0], operands[1]);
     case 5:
-      operands[1] = adj_offsettable_operand (operands[0], 4);
-      operands[2] = adj_offsettable_operand (operands[0], 8);
-      operands[3] = adj_offsettable_operand (operands[0], 12);
-      return \"st	g14,%0\;st	g14,%1\;st	g14,%2\;st	g14,%3\";
+      return i960_output_move_quad_zero (operands[0]);
     }
 }"
   [(set_attr "type" "move,move,load,load,store,store")])