[AArch64] Peephole for SUBS

	* config/aarch64/aarch64.c (define_peephole2 above
	*sub_<shift>_<mode>): New peephole.

	* gcc.target/aarch64/subs_compare_1.c: New test.

From-SVN: r248869

gcc/ChangeLog

+2017-06-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64.c (define_peephole2 above
+	*sub_<shift>_<mode>): New peephole.
+
 2017-05-23  Jan Hubicka  <hubicka@ucw.cz>
 
 	* config/i386/i386.c (make_resolver_func): Update.

gcc/config/aarch64/aarch64.md

@@ -2234,6 +2234,24 @@
   [(set_attr "type" "alus_sreg")]
 )
 
+(define_peephole2
+  [(set (match_operand:GPI 0 "register_operand")
+	(minus:GPI (match_operand:GPI 1 "aarch64_reg_or_zero")
+		    (match_operand:GPI 2 "aarch64_reg_or_zero")))
+   (set (reg:CC CC_REGNUM)
+	(compare:CC
+	  (match_dup 1)
+	  (match_dup 2)))]
+  "!reg_overlap_mentioned_p (operands[0], operands[1])
+   && !reg_overlap_mentioned_p (operands[0], operands[2])"
+  [(const_int 0)]
+  {
+    emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1],
+					 operands[2]));
+    DONE;
+  }
+)
+
 (define_insn "*sub_<shift>_<mode>"
   [(set (match_operand:GPI 0 "register_operand" "=r")
 	(minus:GPI (match_operand:GPI 3 "register_operand" "r")

gcc/testsuite/ChangeLog

+2017-06-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* gcc.target/aarch64/subs_compare_1.c: New test.
+
 2017-06-05  Chenghua Xu  <paul.hua.gm@gmail.com>
 
 	* gcc.target/mips/div-9.c: Delete duplicate test.

gcc/testsuite/gcc.target/aarch64/subs_compare_1.c

+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+foo (int a, int b)
+{
+  int x = a - b;
+  if (a <= b)
+    return x;
+  else
+    return 0;
+}
+
+/* { dg-final { scan-assembler-times "subs\\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-not "cmp\\tw\[0-9\]+, w\[0-9\]+" } } */