rs6000.c (optimization_options): Decorate 'level' as ATTRIBUTE_UNUSED.

	* rs6000.c (optimization_options): Decorate 'level' as
	ATTRIBUTE_UNUSED.
	(mask64_operand): Remove sign-extend thinko.
	(rldic_operand): New function.
	(load_multiple_operation): regno's are unsigned ints.
	(store_multiple_operation): Likewise.
	(lmw_operation): Likewise.
	(stmw_operation): Likewise.
	(includes_lshift_p): shift_mask is unsigned int.
	(includes_lshift64_p): New function.
	(addrs_ok_for_quad_peep): unsigned int reg1.
	(print_operand): Consistently add "else" after
	output_operand_lossage().
	(print_operand, case 'b'): Fold in case 'W'.
	(print_operand, case 'W'): Print rldic MB value.
	(output_epilogue): Update Objective-C language string.
	(output_toc): unsigned HOST_WIDE_INT low, compare unsigned.
	* rs6000.h (PREDICATE_CODES): Add rldic_operand.
	* rs6000.md (ashldi3): Add rldic instruction.
	(iordi3, xordi3): Remove redundant "else if CONST_DOUBLE".
	(cmpsi_internal2, cmpdi_interal2): Use 'b' output template
	modifier.

From-SVN: r35570

gcc/ChangeLog

+2000-08-08  David Edelsohn  <edelsohn@gnu.org>
+
+	* rs6000.c (optimization_options): Decorate 'level' as
+	ATTRIBUTE_UNUSED. 
+	(mask64_operand): Remove sign-extend thinko.
+	(rldic_operand): New function.
+	(load_multiple_operation): regno's are unsigned ints.
+	(store_multiple_operation): Likewise.
+	(lmw_operation): Likewise.
+	(stmw_operation): Likewise.
+	(includes_lshift_p): shift_mask is unsigned int.
+	(includes_lshift64_p): New function.
+	(addrs_ok_for_quad_peep): unsigned int reg1.
+	(print_operand): Consistently add "else" after
+	output_operand_lossage().
+	(print_operand, case 'b'): Fold in case 'W'.
+	(print_operand, case 'W'): Print rldic MB value.
+	(output_epilogue): Update Objective-C language string.
+	(output_toc): unsigned HOST_WIDE_INT low, compare unsigned.
+	* rs6000.h (PREDICATE_CODES): Add rldic_operand.
+	* rs6000.md (ashldi3): Add rldic instruction.
+	(iordi3, xordi3): Remove redundant "else if CONST_DOUBLE".
+	(cmpsi_internal2, cmpdi_interal2): Use 'b' output template
+	modifier.
+
 2000-08-08  Richard Henderson  <rth@cygnus.com>
 
 	* config/ia64/ia64-protos.h: Remove duplicates.  Update
@@ -827,7 +852,7 @@ Wed Aug  2 15:59:34 MET DST 2000  Jan Hubicka  <jh@suse.cz>
 	(f_options): Added dce entry.
 	* invoke.texi: Document -fdce.  Emphasize experimental status of
 	-fssa.
-	* dce: New file.
+	* dce.c: New file.
 
 2000-08-01  Zack Weinberg  <zack@wolery.cumb.org>
 

gcc/config/rs6000/rs6000-protos.h

@@ -56,6 +56,7 @@ extern int non_logical_cint_operand PARAMS ((rtx, enum machine_mode));
 extern int logical_operand PARAMS ((rtx, enum machine_mode));
 extern int mask_operand PARAMS ((rtx, enum machine_mode));
 extern int mask64_operand PARAMS ((rtx, enum machine_mode));
+extern int rldic_operand PARAMS ((rtx, enum machine_mode));
 extern int and64_operand PARAMS ((rtx, enum machine_mode));
 extern int and_operand PARAMS ((rtx, enum machine_mode));
 extern int count_register_operand PARAMS ((rtx, enum machine_mode));
@@ -78,6 +79,7 @@ extern int boolean_operator PARAMS ((rtx, enum machine_mode));
 extern int boolean_or_operator PARAMS ((rtx, enum machine_mode));
 extern int includes_lshift_p PARAMS ((rtx, rtx));
 extern int includes_rshift_p PARAMS ((rtx, rtx));
+extern int includes_lshift64_p PARAMS ((rtx, rtx));
 extern int registers_ok_for_quad_peep PARAMS ((rtx, rtx));
 extern int addrs_ok_for_quad_peep PARAMS ((rtx, rtx));
 extern enum reg_class secondary_reload_class PARAMS ((enum reg_class,

gcc/config/rs6000/rs6000.h

@@ -2757,6 +2757,7 @@ do {									\
   {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}},	\
   {"mask_operand", {CONST_INT}},				\
   {"mask64_operand", {CONST_INT, CONST_DOUBLE}},		\
+  {"rldic_operand", {CONST_INT, CONST_DOUBLE}},			\
   {"count_register_operand", {REG}},				\
   {"xer_operand", {REG}},					\
   {"call_operand", {SYMBOL_REF, REG}},				\

gcc/config/rs6000/rs6000.md

@@ -6664,7 +6664,7 @@
     FAIL;
 }")
 
-(define_insn ""
+(define_insn "*ashldi3_internal1"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
 		   (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
@@ -6672,7 +6672,7 @@
   "sld%I2 %0,%1,%H2"
   [(set_attr "length" "8")])
   
-(define_insn ""
+(define_insn "*ashldi3_internal2"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
 	(compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 			       (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
@@ -6699,7 +6699,7 @@
 		    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_insn "*ashldi3_internal3"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
 	(compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 			       (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
@@ -6728,27 +6728,25 @@
 		    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_insn "*ashldi3_internal4"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
 			   (match_operand:SI 2 "const_int_operand" "i"))
-		(match_operand:DI 3 "mask64_operand" "S")))]
-  "((GET_CODE (operands[3]) == CONST_INT
-     ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
-  "rldic %0,%1,%H2,%S3")
+		(match_operand:DI 3 "rldic_operand" "n")))]
+  "includes_lshift64_p (operands[2], operands[3])"
+  "rldic %0,%1,%H2,%W3")
 
-(define_insn ""
+(define_insn "ashldi3_internal5"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 			    (match_operand:SI 2 "const_int_operand" "i,i"))
-		 (match_operand:DI 3 "mask64_operand" "S,S"))
+		 (match_operand:DI 3 "rldic_operand" "n,n"))
 	 (const_int 0)))
    (clobber (match_scratch:DI 4 "=r,r"))]
-  "((GET_CODE (operands[3]) == CONST_INT
-     ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
+  "includes_lshift64_p (operands[2], operands[3])"
   "@
-   rldic. %0,%1,%H2,%S3
+   rldic. %4,%1,%H2,%W3
    #"
   [(set_attr "type" "delayed_compare")
    (set_attr "length" "4,8")])
@@ -6758,33 +6756,30 @@
 	(compare:CC
 	 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
 			    (match_operand:SI 2 "const_int_operand" ""))
-		 (match_operand:DI 3 "mask64_operand" ""))
+		 (match_operand:DI 3 "rldic_operand" ""))
 	 (const_int 0)))
    (clobber (match_scratch:DI 4 ""))]
-  "((GET_CODE (operands[3]) == CONST_INT
-     ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1
-   && reload_completed"
+  "includes_lshift64_p (operands[2], operands[3]) && reload_completed"
   [(set (match_dup 4)
 	(and:DI (ashift:DI (match_dup 1) (match_dup 2))
-		 (match_dup 3)))
+		(match_dup 3)))
    (set (match_dup 0)
 	(compare:CC (match_dup 4)
 		    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_insn "*ashldi3_internal6"
   [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 			    (match_operand:SI 2 "const_int_operand" "i,i"))
-		 (match_operand:DI 3 "mask64_operand" "S,S"))
+		    (match_operand:DI 3 "rldic_operand" "n,n"))
 	 (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
 	(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "((GET_CODE (operands[3]) == CONST_INT
-     ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1"
+  "includes_lshift64_p (operands[2], operands[3])"
   "@
-   rldic. %0,%1,%H2,%S3
+   rldic. %0,%1,%H2,%W3
    #"
   [(set_attr "type" "delayed_compare")
    (set_attr "length" "4,8")])
@@ -6794,15 +6789,14 @@
 	(compare:CC
 	 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
 			    (match_operand:SI 2 "const_int_operand" ""))
-		 (match_operand:DI 3 "mask64_operand" ""))
+		 (match_operand:DI 3 "rldic_operand" ""))
 	 (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
 	(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "((GET_CODE (operands[3]) == CONST_INT
-     ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1
-   && reload_completed"
+  "includes_lshift64_p (operands[2], operands[3]) && reload_completed"
   [(set (match_dup 0)
-	(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
+	(and:DI (ashift:DI (match_dup 1) (match_dup 2))
+		(match_dup 3)))
    (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
@@ -6826,14 +6820,14 @@
     FAIL;
 }")
 
-(define_insn ""
+(define_insn "*lshrdi3_internal1"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
 		     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
   "TARGET_POWERPC64"
   "srd%I2 %0,%1,%H2")
 
-(define_insn ""
+(define_insn "*lshrdi3_internal2"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
 	(compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
@@ -6860,7 +6854,7 @@
 		    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_insn "*lshrdi3_internal3"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
 	(compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
@@ -6907,14 +6901,14 @@
     FAIL;
 }")
 
-(define_insn ""
+(define_insn "*ashrdi3_internal1"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
 		     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
   "TARGET_POWERPC64"
   "srad%I2 %0,%1,%H2")
 
-(define_insn ""
+(define_insn "*ashrdi3_internal2"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
 	(compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
@@ -6941,7 +6935,7 @@
 		    (const_int 0)))]
   "")
 
-(define_insn ""
+(define_insn "*ashrdi3_internal3"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
 	(compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
@@ -7076,7 +7070,7 @@
 	  emit_insn (gen_iordi3 (tmp, operands[1],
 				 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
 	}
-      else if (GET_CODE (operands[2]) == CONST_DOUBLE)
+      else
         {
 	  value = CONST_DOUBLE_LOW (operands[2]);
 	  emit_insn (gen_iordi3 (tmp, operands[1],
@@ -7084,6 +7078,7 @@
 						     & (~ (HOST_WIDE_INT) 0xffff),
 						     0, DImode)));
 	}
+
       emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
       DONE;
     }
@@ -7108,7 +7103,7 @@
 	  emit_insn (gen_xordi3 (tmp, operands[1],
 				 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
 	}
-      else if (GET_CODE (operands[2]) == CONST_DOUBLE)
+      else
         {
 	  value = CONST_DOUBLE_LOW (operands[2]);
 	  emit_insn (gen_xordi3 (tmp, operands[1],
@@ -7116,6 +7111,7 @@
 						     & (~ (HOST_WIDE_INT) 0xffff),
 						     0, DImode)));
 	}
+
       emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
       DONE;
     }
@@ -10424,7 +10420,7 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32);
 	(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
   ""
-  "{cmpl%I2|cmplw%I2} %0,%1,%W2"
+  "{cmpl%I2|cmplw%I2} %0,%1,%b2"
   [(set_attr "type" "compare")])
 
 (define_insn "*cmpdi_internal2"
@@ -10432,7 +10428,7 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32);
 	(compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
 		       (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
   ""
-  "cmpld%I2 %0,%1,%W2"
+  "cmpld%I2 %0,%1,%b2"
   [(set_attr "type" "compare")])
 
 ;; The following two insns don't exist as single insns, but if we provide