Several instructions disassemble a zero immediate as wzr/xzr due to using a…

Several instructions disassemble a zero immediate as wzr/xzr due to using a register operand in the disassembly.

Several instructions disassemble a zero immediate as wzr/xzr due to
using a register operand in the disassembly.  Avoid this by removing
the register operand.

2016-01-28  Wilco Dijkstra  <wdijkstr@arm.com>

	* config/aarch64/aarch64.md (ccmp<mode>): Disassemble
	immediate as %1.
	(add<mode>3_compare0): Likewise.
	(addsi3_compare0_uxtw): Likewise.
	(add<mode>3nr_compare0): Likewise.
	(compare_neg<mode>): Likewise.
	(<optab><mode>3): Likewise.

From-SVN: r232921

gcc/ChangeLog

+2016-01-28  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/aarch64/aarch64.md (ccmp<mode>): Disassemble
+	immediate as %1.
+	(add<mode>3_compare0): Likewise.
+	(addsi3_compare0_uxtw): Likewise.
+	(add<mode>3nr_compare0): Likewise.
+	(compare_neg<mode>): Likewise.
+	(<optab><mode>3): Likewise.
+
 2016-01-28  Ilya Enkovich  <enkovich.gnu@gmail.com>
 
 	* tree-vect-stmts.c (vectorizable_comparison): Add

gcc/config/aarch64/aarch64.md

@@ -285,7 +285,7 @@
   ""
   "@
    ccmp\\t%<w>2, %<w>3, %k5, %m4
-   ccmp\\t%<w>2, %<w>3, %k5, %m4
+   ccmp\\t%<w>2, %3, %k5, %m4
    ccmn\\t%<w>2, #%n3, %k5, %m4"
   [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
 )
@@ -1733,7 +1733,7 @@
   ""
   "@
   adds\\t%<w>0, %<w>1, %<w>2
-  adds\\t%<w>0, %<w>1, %<w>2
+  adds\\t%<w>0, %<w>1, %2
   subs\\t%<w>0, %<w>1, #%n2"
   [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
 )
@@ -1750,7 +1750,7 @@
   ""
   "@
   adds\\t%w0, %w1, %w2
-  adds\\t%w0, %w1, %w2
+  adds\\t%w0, %w1, %2
   subs\\t%w0, %w1, #%n2"
   [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
 )
@@ -1932,7 +1932,7 @@
   ""
   "@
   cmn\\t%<w>0, %<w>1
-  cmn\\t%<w>0, %<w>1
+  cmn\\t%<w>0, %1
   cmp\\t%<w>0, #%n1"
   [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
 )
@@ -2878,7 +2878,7 @@
   ""
   "@
    cmp\\t%<w>0, %<w>1
-   cmp\\t%<w>0, %<w>1
+   cmp\\t%<w>0, %1
    cmn\\t%<w>0, #%n1"
   [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
 )
@@ -3312,7 +3312,7 @@
   ""
   "@
   <logical>\\t%<w>0, %<w>1, %<w>2
-  <logical>\\t%<w>0, %<w>1, %<w>2
+  <logical>\\t%<w>0, %<w>1, %2
   <logical>\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
   [(set_attr "type" "logic_reg,logic_imm,neon_logic")
    (set_attr "simd" "*,*,yes")]