Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
R
riscv-gcc-1
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
riscv-gcc-1
Commits
e26f388a
Commit
e26f388a
authored
Nov 10, 1993
by
Richard Kenner
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
(reload patterns for mla instruction): New.
From-SVN: r6060
parent
6412a77e
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
56 additions
and
0 deletions
+56
-0
gcc/config/arm/arm.md
+56
-0
No files found.
gcc/config/arm/arm.md
View file @
e26f388a
...
@@ -4136,6 +4136,62 @@
...
@@ -4136,6 +4136,62 @@
}"
}"
[
(set_attr "conds" "set")
[
(set_attr "conds" "set")
(set_attr "length" "5")])
(set_attr "length" "5")])
;; These are similar, but are needed when the mla pattern contains the
;; eliminated register as operand 3.
(define_insn ""
[
(set (match_operand:SI 0 "" "=&r,&r")
(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "" "%0,r")
(match_operand:SI 2 "" "r,r"))
(match_operand:SI 3 "" "r,r"))
(match_operand:SI 4 "const_int_operand" "n,n")))]
"reload_in_progress"
"
*
arm_output_asm_insn (
\"
mla
\\
t%0, %2, %1, %3
\"
, operands);
operands
[
2
]
= operands
[
4
]
;
operands
[
1
]
= operands
[
0
]
;
return output_add_immediate (operands);
"
[
(set_attr "length" "5")
]
)
(define_insn ""
[
(set (reg:CC_NOOV 24)
(compare:CC_NOOV (plus:SI (plus:SI (mult:SI
(match_operand:SI 3 "" "r")
(match_operand:SI 4 "" "r"))
(match_operand:SI 1 "" "r"))
(match_operand:SI 2 "const_int_operand" "n"))
(const_int 0)))
(set (match_operand:SI 0 "" "=&r")
(plus:SI (plus:SI (mult:SI (match_dup 3) (match_dup 4)) (match_dup 1))
(match_dup 2)))]
"reload_in_progress"
"
*
output_add_immediate (operands);
return arm_output_asm_insn (
\"
mlas
\\
t%0, %3, %4, %0
\"
, operands);
"
[
(set_attr "length" "5")
(set_attr "conds" "set")])
(define_insn ""
[
(set (reg:CC_NOOV 24)
(compare:CC_NOOV (plus:SI (plus:SI (mult:SI
(match_operand:SI 3 "" "r")
(match_operand:SI 4 "" "r"))
(match_operand:SI 1 "" "r"))
(match_operand:SI 2 "const_int_operand" "n"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=&r"))]
"reload_in_progress"
"
*
output_add_immediate (operands);
return arm_output_asm_insn (
\"
mlas
\\
t%0, %3, %4, %0
\"
, operands);
"
[
(set_attr "length" "5")
(set_attr "conds" "set")])
(define_insn ""
(define_insn ""
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment