Commit e18b4a81 by Yufeng Zhang Committed by Yufeng Zhang

aarch64.c (aarch64_force_temporary): Add an extra parameter 'mode' of type 'enum…

aarch64.c (aarch64_force_temporary): Add an extra parameter 'mode' of type 'enum machine_mode mode'...

gcc/

	* config/aarch64/aarch64.c (aarch64_force_temporary): Add an extra
	parameter 'mode' of type 'enum machine_mode mode'; change to pass
	'mode' to force_reg.
	(aarch64_add_offset): Update calls to aarch64_force_temporary.
	(aarch64_expand_mov_immediate): Likewise.

From-SVN: r200467
parent 9c023bf0
2013-06-27 Yufeng Zhang <yufeng.zhang@arm.com> 2013-06-27 Yufeng Zhang <yufeng.zhang@arm.com>
* config/aarch64/aarch64.c (aarch64_force_temporary): Add an extra
parameter 'mode' of type 'enum machine_mode mode'; change to pass
'mode' to force_reg.
(aarch64_add_offset): Update calls to aarch64_force_temporary.
(aarch64_expand_mov_immediate): Likewise.
2013-06-27 Yufeng Zhang <yufeng.zhang@arm.com>
* config/aarch64/aarch64.c (aarch64_add_offset): Change to pass * config/aarch64/aarch64.c (aarch64_add_offset): Change to pass
'mode' to aarch64_plus_immediate and gen_rtx_PLUS. 'mode' to aarch64_plus_immediate and gen_rtx_PLUS.
......
...@@ -789,10 +789,10 @@ aarch64_split_simd_move (rtx dst, rtx src) ...@@ -789,10 +789,10 @@ aarch64_split_simd_move (rtx dst, rtx src)
} }
static rtx static rtx
aarch64_force_temporary (rtx x, rtx value) aarch64_force_temporary (enum machine_mode mode, rtx x, rtx value)
{ {
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
return force_reg (Pmode, value); return force_reg (mode, value);
else else
{ {
x = aarch64_emit_move (x, value); x = aarch64_emit_move (x, value);
...@@ -811,8 +811,9 @@ aarch64_add_offset (enum machine_mode mode, rtx temp, rtx reg, HOST_WIDE_INT off ...@@ -811,8 +811,9 @@ aarch64_add_offset (enum machine_mode mode, rtx temp, rtx reg, HOST_WIDE_INT off
might be improvable in the future. */ might be improvable in the future. */
high = GEN_INT (offset); high = GEN_INT (offset);
offset = 0; offset = 0;
high = aarch64_force_temporary (temp, high); high = aarch64_force_temporary (mode, temp, high);
reg = aarch64_force_temporary (temp, gen_rtx_PLUS (mode, high, reg)); reg = aarch64_force_temporary (mode, temp,
gen_rtx_PLUS (mode, high, reg));
} }
return plus_constant (mode, reg, offset); return plus_constant (mode, reg, offset);
} }
...@@ -851,7 +852,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm) ...@@ -851,7 +852,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
&& targetm.cannot_force_const_mem (mode, imm)) && targetm.cannot_force_const_mem (mode, imm))
{ {
gcc_assert(can_create_pseudo_p ()); gcc_assert(can_create_pseudo_p ());
base = aarch64_force_temporary (dest, base); base = aarch64_force_temporary (mode, dest, base);
base = aarch64_add_offset (mode, NULL, base, INTVAL (offset)); base = aarch64_add_offset (mode, NULL, base, INTVAL (offset));
aarch64_emit_move (dest, base); aarch64_emit_move (dest, base);
return; return;
...@@ -868,7 +869,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm) ...@@ -868,7 +869,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
if (offset != const0_rtx) if (offset != const0_rtx)
{ {
gcc_assert(can_create_pseudo_p ()); gcc_assert(can_create_pseudo_p ());
base = aarch64_force_temporary (dest, base); base = aarch64_force_temporary (mode, dest, base);
base = aarch64_add_offset (mode, NULL, base, INTVAL (offset)); base = aarch64_add_offset (mode, NULL, base, INTVAL (offset));
aarch64_emit_move (dest, base); aarch64_emit_move (dest, base);
return; return;
......
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