Enable VAES support [2/5]

gcc/
	* config.gcc: Add vaesintrin.h.
	* config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI_V64QI): New type.
	* config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi,
	__builtin_ia32_vaesdec_v32qi, __builtin_ia32_vaesdec_v64qi): New builtins.
	* config/i386/i386.c (ix86_expand_args_builtin): Handle new type.
	* config/i386/immintrin.h: Include vaesintrin.h.
	* config/i386/sse.md (vaesdec_<mode>): New pattern.
	* config/i386/vaesintrin.h (_mm256_aesdec_epi128, _mm512_aesdec_epi128,
	_mm_aesdec_epi128): New intrinsics.

gcc/testsuite/
	* gcc.target/i386/avx512-check.h: Handle bit_VAES.
	* gcc.target/i386/avx512f-aesdec-2.c: New test.
	* gcc.target/i386/avx512fvl-vaes-1.c: Ditto.
	* gcc.target/i386/avx512vl-aesdec-2.c: Ditto.
	* gcc.target/i386/i386.exp (check_effective_target_avx512vaes): New.

From-SVN: r255572

gcc/ChangeLog

 2017-12-12  Julia Koval  <julia.koval@intel.com>
 
+	* config.gcc: Add vaesintrin.h.
+	* config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI_V64QI): New type.
+	* config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi,
+	__builtin_ia32_vaesdec_v32qi, __builtin_ia32_vaesdec_v64qi): New builtins.
+	* config/i386/i386.c (ix86_expand_args_builtin): Handle new type.
+	* config/i386/immintrin.h: Include vaesintrin.h.
+	* config/i386/sse.md (vaesdec_<mode>): New pattern.
+	* config/i386/vaesintrin.h (_mm256_aesdec_epi128, _mm512_aesdec_epi128,
+	_mm_aesdec_epi128): New intrinsics.
+
+2017-12-12  Julia Koval  <julia.koval@intel.com>
+
 	* common/config/i386/i386-common.c (OPTION_MASK_ISA_VAES_SET,
 	OPTION_MASK_ISA_VAES_UNSET): New.
 	(ix86_handle_option): Handle -mvaes.

gcc/config.gcc

@@ -381,7 +381,7 @@ i[34567]86-*-*)
 		       clzerointrin.h pkuintrin.h sgxintrin.h cetintrin.h
 		       gfniintrin.h cet.h avx512vbmi2intrin.h
 		       avx512vbmi2vlintrin.h avx512vnniintrin.h
-		       avx512vnnivlintrin.h"
+		       avx512vnnivlintrin.h gfniintrin.h vaesintrin.h"
 	;;
 x86_64-*-*)
 	cpu_type=i386
@@ -408,7 +408,7 @@ x86_64-*-*)
 		       clzerointrin.h pkuintrin.h sgxintrin.h cetintrin.h
 		       gfniintrin.h cet.h avx512vbmi2intrin.h
 		       avx512vbmi2vlintrin.h avx512vnniintrin.h
-		       avx512vnnivlintrin.h"
+		       avx512vnnivlintrin.h gfniintrin.h vaesintrin.h"
 	;;
 ia64-*-*)
 	extra_headers=ia64intrin.h

gcc/config/i386/i386-builtin.def

@@ -2763,6 +2763,11 @@ BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssds_v4si, "__builtin_ia32_vpdp
 BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssds_v4si_mask, "__builtin_ia32_vpdpwssds_v4si_mask", IX86_BUILTIN_VPDPWSSDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT)
 BDESC (OPTION_MASK_ISA_AVX512VNNI, CODE_FOR_vpdpwssds_v4si_maskz, "__builtin_ia32_vpdpwssds_v4si_maskz", IX86_BUILTIN_VPDPWSSDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT)
 
+/* VAES */
+BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdec_v16qi, "__builtin_ia32_vaesdec_v16qi", IX86_BUILTIN_VAESDEC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
+BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdec_v32qi, "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI)
+BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
+
 BDESC_END (ARGS2, SPECIAL_ARGS2)
 
 BDESC_FIRST (special_args2, SPECIAL_ARGS2, OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_compressstorev64qi_mask, "__builtin_ia32_compressstoreuqi512_mask", IX86_BUILTIN_PCOMPRESSBSTORE512, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_UDI)

gcc/config/i386/immintrin.h

@@ -102,6 +102,8 @@
 
 #include <gfniintrin.h>
 
+#include <vaesintrin.h>
+
 #ifndef __RDRND__
 #pragma GCC push_options
 #pragma GCC target("rdrnd")

gcc/config/i386/sse.md

@@ -172,6 +172,9 @@
   UNSPEC_VPMADDUBSWACCSSD
   UNSPEC_VPMADDWDACCD
   UNSPEC_VPMADDWDACCSSD
+
+  ;; For VAES support
+  UNSPEC_VAESDEC
 ])
 
 (define_c_enum "unspecv" [
@@ -374,6 +377,9 @@
 (define_mode_iterator VI2_AVX512VL
   [(V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") V32HI])
 
+(define_mode_iterator VI1_AVX512VL_F
+  [V32QI (V16QI "TARGET_AVX512VL") (V64QI "TARGET_AVX512F")])
+
 (define_mode_iterator VI8_AVX2_AVX512BW
   [(V8DI "TARGET_AVX512BW") (V4DI "TARGET_AVX2") V2DI])
 
@@ -20449,3 +20455,13 @@
   "TARGET_AVX512VNNI"
   "vpdpwssds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
+
+(define_insn "vaesdec_<mode>"
+  [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
+	  (unspec:VI1_AVX512VL_F
+	  [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
+	   (match_operand:VI1_AVX512VL_F 2 "vector_operand" "v")]
+	  UNSPEC_VAESDEC))]
+  "TARGET_VAES"
+  "vaesdec\t{%2, %1, %0|%0, %1, %2}"
+)

gcc/config/i386/vaesintrin.h

+#ifndef __VAESINTRIN_H_INCLUDED
+#define __VAESINTRIN_H_INCLUDED
+
+#ifndef __VAES__
+#pragma GCC push_options
+#pragma GCC target("vaes")
+#define __DISABLE_VAES__
+#endif /* __VAES__ */
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_aesdec_epi128 (__m256i __A, __m256i __B)
+{
+  return (__m256i)__builtin_ia32_vaesdec_v32qi ((__v32qi) __A, (__v32qi) __B);
+}
+
+#ifdef __DISABLE_VAES__
+#undef __DISABLE_VAES__
+#pragma GCC pop_options
+#endif /* __DISABLE_VAES__ */
+
+
+#if !defined(__VAES__) || !defined(__AVX512F)
+#pragma GCC push_options
+#pragma GCC target("vaes,avx512f")
+#define __DISABLE_VAESF__
+#endif /* __VAES__ */
+
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_aesdec_epi128 (__m512i __A, __m512i __B)
+{
+  return (__m512i)__builtin_ia32_vaesdec_v64qi ((__v64qi) __A, (__v64qi) __B);
+}
+
+#ifdef __DISABLE_VAESF__
+#undef __DISABLE_VAESF__
+#pragma GCC pop_options
+#endif /* __DISABLE_VAES__ */
+
+#if !defined(__VAES__) || !defined(__AVX512VL)
+#pragma GCC push_options
+#pragma GCC target("vaes,avx512vl")
+#define __DISABLE_VAESVL__
+#endif /* __VAES__ */
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_aesdec_epi128 (__m128i __A, __m128i __B)
+{
+  return (__m128i)__builtin_ia32_vaesdec_v16qi ((__v16qi) __A, (__v16qi) __B);
+}
+
+#ifdef __DISABLE_VAESVL__
+#undef __DISABLE_VAESVL__
+#pragma GCC pop_options
+#endif /* __DISABLE_VAES__ */
+#endif /* __VAESINTRIN_H_INCLUDED */

gcc/testsuite/ChangeLog

+2017-12-12  Julia Koval  <julia.koval@intel.com>
+
+	* gcc.target/i386/avx512-check.h: Handle bit_VAES.
+	* gcc.target/i386/avx512f-aesdec-2.c: New test.
+	* gcc.target/i386/avx512fvl-vaes-1.c: Ditto.
+	* gcc.target/i386/avx512vl-aesdec-2.c: Ditto.
+	* gcc.target/i386/i386.exp (check_effective_target_avx512vaes): New.
+
 2017-12-11  David Malcolm  <dmalcolm@redhat.com>
 
 	PR c/82050

gcc/testsuite/gcc.target/i386/avx512-check.h

@@ -84,6 +84,9 @@ main ()
 #ifdef AVX512VNNI
       && (ecx & bit_AVX512VNNI)
 #endif
+#ifdef VAES
+      && (ecx & bit_VAES)
+#endif
       && avx512f_os_support ())
     {
       DO_TEST ();

gcc/testsuite/gcc.target/i386/avx512f-aesdec-2.c

+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -mvaes" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target avx512vaes } */
+
+#define AVX512F
+
+#define VAES
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+
+#include "avx512f-mask-type.h"
+
+static void
+CALC (unsigned int *r)
+{
+  for (int i = 0; i < SIZE; i+=4)
+    {
+      r[i] = 0xba0cda94;
+      r[i + 1] = 0x73676a7;
+      r[i + 2] = 0xd3204422;
+      r[i + 3] = 0x5506edd;
+    }
+}
+
+void
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_ud) res1, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned int res_ref[SIZE];
+
+  for (int i = 0; i < SIZE; i+=4)
+    {
+      src1.a[i] = 0x5d53475d;
+      src1.a[i + 1] = 0x63746f72;
+      src1.a[i + 2] = 0x73745665;
+      src1.a[i + 3] = 0x7b5b5465;
+      src2.a[i] = 0x726f6e5d;
+      src2.a[i + 1] = 0x5b477565;
+      src2.a[i + 2] = 0x68617929;
+      src2.a[i + 3] = 0x48692853;
+    }
+
+  CALC (res_ref);
+  res1.x = INTRINSIC (_aesdec_epi128) (src2.x, src1.x);
+
+  if (UNION_CHECK (AVX512F_LEN, i_ud) (res1, res_ref))
+    abort ();
+}

gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c

+/* { dg-do compile } */
+/* { dg-options "-mvaes -mavx512f -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)"  1 } } */
+
+/* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)"  1 } } */
+
+/* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)"  1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x,y;
+volatile __m256i x256, y256;
+volatile __m128i x128, y128;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_aesdec_epi128 (x, y);
+
+  x256 = _mm256_aesdec_epi128 (x256, y256);
+
+  x128 = _mm_aesdec_epi128 (x128, y128);
+
+}

gcc/testsuite/gcc.target/i386/avx512vl-aesdec-2.c

+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512bw -mavx512vl -mvaes" } */
+/* { dg-require-effective-target avx512vl } */
+/* { dg-require-effective-target avx512bw } */
+/* { dg-require-effective-target avx512vaes } */
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512f-aesdec-2.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512f-aesdec-2.c"

gcc/testsuite/gcc.target/i386/i386.exp

@@ -456,6 +456,20 @@ proc check_effective_target_avx512vnni { } {
     } "-mavx512vnni -mavx512f" ]
 }
 
+# Return 1 if vaes instructions can be compiled.
+proc check_effective_target_avx512vaes { } {
+    return [check_no_compiler_messages avx512vaes object {
+
+        typedef int __v16si __attribute__ ((__vector_size__ (64)));
+
+	__v32qi
+	_mm256_aesdec_epi128 (__v32qi __A, __v32qi __B)
+	{
+	  return (__v32qi)__builtin_ia32_vaesdec_v32qi ((__v32qi) __A, (__v32qi) __B);
+	}
+    } "-mvaes" ]
+}
+
 # If a testcase doesn't have special options, use these.
 global DEFAULT_CFLAGS
 if ![info exists DEFAULT_CFLAGS] then {