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extend.texi (Half-Precision): Update wording to reflect that there are now… 

extend.texi (Half-Precision): Update wording to reflect that there are now multiple -mfpu options that enable...

2009-11-09  Paul Brook  <paul@codesourcery.com>
	Daniel Jacobowitz  <dan@codesourcery.com>
	Sandra Loosemore  <sandra@codesourcery.com>

	gcc/
	* doc/extend.texi (Half-Precision): Update wording to reflect
	that there are now multiple -mfpu options that enable fp16
	hardware support.
	* doc/invoke.texi: Update list of ARM -mfpu= options.
	* config.gcc: Update ARM --with-fpu option list.
	* config/arm/arm.c (all_fpus): Add vfpv3-fp16, vfpv3-d16-fp16,
	vfpv3xd and vfpv3xd-fp16.
	(use_vfp_abi): New function.
	(aapcs_vfp_is_call_or_return_candidate): Avoid double precision regs
	when undesirable.
	(aapcs_vfp_is_return_candidate, aapcs_vfp_is_call_candidate,
	aapcs_vfp_allocate_return_reg): Use use_vfp_abi.
        (arm_rtx_costs_1, arm_size_rtx_costs, arm_fastmul_rtx_costs,
        arm_9e_rtx_costs): Only expect double-precision operations if the FPU
        provides them.
	(coproc_secondary_reload_class): Reload HFmode via GENERAL_REGS if no
	NEON.
	(arm_print_operand): Handle 'p' modifier.
	(arm_hard_regno_mode_ok): : Allow HFmode in VFP registers if
	TARGET_FP16.
	* config/arm/arm.h (TARGET_VFP_SINGLE, TARGET_VFP_DOUBLE): Define.
	(TARGET_FP16): Define.
	* config/arm/vfp.md: Disable double-precision patterns if the FPU
	does not provide them.
	(arm_movdi_vfp, thumb2_movdi_vfp): Use fcpys to move
	double-precision values on a single-precision FPU.
        (movdf_vfp, thumb2_movdf_vfp): Likewise.  Use "Dy" for
        double-precision constants.
	(movhf_vfp_neon): New pattern (was movhf_vfp).
	(movhf_vfp): Remove NEON instructions.
	* config/arm/constraints.md: Add new "Dy" constraint for
	double-precision constants.  Update description of "Dv".
	* config/arm/arm.md: Disable double-precision patterns if the FPU
	does not provide them


Co-Authored-By: Daniel Jacobowitz <dan@codesourcery.com>
Co-Authored-By: Sandra Loosemore <sandra@codesourcery.com>

From-SVN: r154034
parent 2bf17308
Showing with 187 additions and 66 deletions
gcc/ChangeLog
2009-11-09 Paul Brook <paul@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Sandra Loosemore <sandra@codesourcery.com>
* doc/extend.texi (Half-Precision): Update wording to reflect
that there are now multiple -mfpu options that enable fp16
hardware support.
* doc/invoke.texi: Update list of ARM -mfpu= options.
* config.gcc: Update ARM --with-fpu option list.
* config/arm/arm.c (all_fpus): Add vfpv3-fp16, vfpv3-d16-fp16,
vfpv3xd and vfpv3xd-fp16.
(use_vfp_abi): New function.
(aapcs_vfp_is_call_or_return_candidate): Avoid double precision regs
when undesirable.
(aapcs_vfp_is_return_candidate, aapcs_vfp_is_call_candidate,
aapcs_vfp_allocate_return_reg): Use use_vfp_abi.
(arm_rtx_costs_1, arm_size_rtx_costs, arm_fastmul_rtx_costs,
arm_9e_rtx_costs): Only expect double-precision operations if the FPU
provides them.
(coproc_secondary_reload_class): Reload HFmode via GENERAL_REGS if no
NEON.
(arm_print_operand): Handle 'p' modifier.
(arm_hard_regno_mode_ok): : Allow HFmode in VFP registers if
TARGET_FP16.
* config/arm/arm.h (TARGET_VFP_SINGLE, TARGET_VFP_DOUBLE): Define.
(TARGET_FP16): Define.
* config/arm/vfp.md: Disable double-precision patterns if the FPU
does not provide them.
(arm_movdi_vfp, thumb2_movdi_vfp): Use fcpys to move
double-precision values on a single-precision FPU.
(movdf_vfp, thumb2_movdf_vfp): Likewise. Use "Dy" for
double-precision constants.
(movhf_vfp_neon): New pattern (was movhf_vfp).
(movhf_vfp): Remove NEON instructions.
* config/arm/constraints.md: Add new "Dy" constraint for
double-precision constants. Update description of "Dv".
* config/arm/arm.md: Disable double-precision patterns if the FPU
does not provide them
2009-11-09 Jakub Jelinek <jakub@redhat.com>
* config/i386/i386.c (print_operand) <case 'D'>: Fix formatting.
gcc/config.gcc
......@@ -2817,7 +2817,7 @@ case "${target}" in
case "$with_fpu" in
"" \
| fpa | fpe2 | fpe3 | maverick | vfp | vfp3 | neon )
| fpa | fpe2 | fpe3 | maverick | vfp | vfp3 | vfpv3 | vfpv3-fp16 | vfpv3-d16 | vfpv3-d16-fp16 | vfpv3xd | vfpv3xd-fp16 | neon | neon-fp16 )
# OK
;;
*)
......
gcc/config/arm/arm.h
......@@ -230,10 +230,19 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
/* FPU supports VFPv3 instructions. */
#define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
/* FPU supports NEON/VFP half-precision floating-point. */
/* FPU only supports VFP single-precision instructions. */
#define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
/* FPU supports VFP double-precision instructions. */
#define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
/* FPU supports half-precision floating-point with NEON element load/store. */
#define TARGET_NEON_FP16 \
(TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
/* FPU supports VFP half-precision floating-point. */
#define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
/* FPU supports Neon instructions. The setting of this macro gets
revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
and TARGET_HARD_FLOAT to ensure that NEON instructions are
......
gcc/config/arm/arm.md
......@@ -958,7 +958,7 @@
[(set (match_operand:DF 0 "s_register_operand" "")
(plus:DF (match_operand:DF 1 "s_register_operand" "")
(match_operand:DF 2 "arm_float_add_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
if (TARGET_MAVERICK
&& !cirrus_fp_register (operands[2], DFmode))
......@@ -1196,7 +1196,7 @@
[(set (match_operand:DF 0 "s_register_operand" "")
(minus:DF (match_operand:DF 1 "arm_float_rhs_operand" "")
(match_operand:DF 2 "arm_float_rhs_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
if (TARGET_MAVERICK)
{
......@@ -1733,7 +1733,7 @@
[(set (match_operand:DF 0 "s_register_operand" "")
(mult:DF (match_operand:DF 1 "s_register_operand" "")
(match_operand:DF 2 "arm_float_rhs_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
if (TARGET_MAVERICK
&& !cirrus_fp_register (operands[2], DFmode))
......@@ -1753,7 +1753,7 @@
[(set (match_operand:DF 0 "s_register_operand" "")
(div:DF (match_operand:DF 1 "arm_float_rhs_operand" "")
(match_operand:DF 2 "arm_float_rhs_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
"")
;; Modulo insns
......@@ -3605,7 +3605,7 @@
(define_expand "negdf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(neg:DF (match_operand:DF 1 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
"")
;; abssi2 doesn't really clobber the condition codes if a different register
......@@ -3691,7 +3691,7 @@
(define_expand "absdf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(abs:DF (match_operand:DF 1 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"")
(define_expand "sqrtsf2"
......@@ -3703,7 +3703,7 @@
(define_expand "sqrtdf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(sqrt:DF (match_operand:DF 1 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
"")
(define_insn_and_split "one_cmpldi2"
......@@ -3814,7 +3814,7 @@
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(float:DF (match_operand:SI 1 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
if (TARGET_MAVERICK)
{
......@@ -3866,7 +3866,7 @@
(define_expand "fix_truncdfsi2"
[(set (match_operand:SI 0 "s_register_operand" "")
(fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
if (TARGET_MAVERICK)
{
......@@ -3883,7 +3883,7 @@
[(set (match_operand:SF 0 "s_register_operand" "")
(float_truncate:SF
(match_operand:DF 1 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
""
)
......@@ -4784,7 +4784,7 @@
(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(float_extend:DF (match_operand:SF 1 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
""
)
......@@ -5971,7 +5971,7 @@
(define_insn "*arm32_movhf"
[(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,r,r")
(match_operand:HF 1 "general_operand" " m,r,r,F"))]
"TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_NEON_FP16)
"TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16)
&& ( s_register_operand (operands[0], HFmode)
|| s_register_operand (operands[1], HFmode))"
"*
......@@ -6682,7 +6682,7 @@
(match_operand:DF 2 "arm_float_compare_operand" "")])
(label_ref (match_operand 3 "" ""))
(pc)))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
operands[3])); DONE;"
)
......@@ -8296,7 +8296,7 @@
(if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
(match_operand:DF 2 "s_register_operand" "")
(match_operand:DF 3 "arm_float_add_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
"
{
enum rtx_code code = GET_CODE (operands[1]);
......
gcc/config/arm/constraints.md
......@@ -29,7 +29,7 @@
;; in Thumb-1 state: I, J, K, L, M, N, O
;; The following multi-letter normal constraints have been used:
;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv
;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy
;; in Thumb-1 state: Pa, Pb
;; The following memory constraints have been used:
......@@ -207,10 +207,17 @@
(define_constraint "Dv"
"@internal
In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
or fconstd instruction."
instruction."
(and (match_code "const_double")
(match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
(define_constraint "Dy"
"@internal
In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
instruction."
(and (match_code "const_double")
(match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
(define_memory_constraint "Ut"
"@internal
In ARM/Thumb-2 state an address valid for loading/storing opaque structure
......
gcc/doc/extend.texi
......@@ -960,8 +960,9 @@ direct conversion.
ARM provides hardware support for conversions between
@code{__fp16} and @code{float} values
as an extension to VFP and NEON (Advanced SIMD). GCC generates
code using the instructions provided by this extension if you compile
with the options @option{-mfpu=neon-fp16 -mfloat-abi=softfp},
code using these hardware instructions if you compile with
options to select an FPU that provides them;
for example, @option{-mfpu=neon-fp16 -mfloat-abi=softfp},
in addition to the @option{-mfp16-format} option to select
a half-precision format.
......
gcc/doc/invoke.texi
......@@ -9788,10 +9788,12 @@ of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
@opindex mfp
This specifies what floating point hardware (or hardware emulation) is
available on the target. Permissible names are: @samp{fpa}, @samp{fpe2},
@samp{fpe3}, @samp{maverick}, @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-d16},
@samp{neon}, and @samp{neon-fp16}. @option{-mfp} and @option{-mfpe}
are synonyms for @option{-mfpu}=@samp{fpe}@var{number}, for compatibility
with older versions of GCC@.
@samp{fpe3}, @samp{maverick}, @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-fp16},
@samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd}, @samp{vfpv3xd-fp16},
@samp{neon}, and @samp{neon-fp16}.
@option{-mfp} and @option{-mfpe} are synonyms for
@option{-mfpu}=@samp{fpe}@var{number}, for compatibility with older versions
of GCC@.
If @option{-msoft-float} is specified this specifies the format of
floating point values.
......
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