rs6000: Remove TARGET_SPE and TARGET_SPE_ABI and friends

	* config/rs6000/rs6000-common.c (rs6000_handle_option): Remove
	SPE ABI handling.
	* config/rs6000/paired.md (paired_negv2sf2): Rename to negv2sf2.
	(paired_absv2sf2, paired_addv2sf3, paired_subv2sf3, paired_mulv2sf3,
	paired_divv2sf3): Similar.
	* config/rs6000/predicates.md: Replace TARGET_SPE, TARGET_SPE_ABI,
	SPE_VECTOR_MODE and SPE_HIGH_REGNO_P by 0; simplify.
	* config/rs6000/rs6000-builtin.def: Delete RS6000_BUILTIN_E and
	RS6000_BUILTIN_S.
	Delete BU_SPE_1, BU_SPE_2, BU_SPE_3, BU_SPE_E, BU_SPE_P, and BU_SPE_X.
	Rename the paired_* instruction patterns.
	* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Do not
	define __SPE__.
	* config/rs6000/rs6000-protos.h (invalid_e500_subreg): Delete.
	* config/rs6000/rs6000.c: Delete RS6000_BUILTIN_E and RS6000_BUILTIN_S.
	(struct rs6000_stack): Delete fields spe_gp_save_offset, spe_gp_size,
	spe_padding_size, and spe_64bit_regs_used.  Replace TARGET_SPE and
	TARGET_SPE_ABI with 0, simplify.  Replace SPE_VECTOR_MODE with
	PAIRED_VECTOR_MODE.
	(struct machine_function): Delete field spe_insn_chain_scanned_p.
	(spe_func_has_64bit_regs_p): Delete.
	(spe_expand_predicate_builtin): Delete.
	(spe_expand_evsel_builtin): Delete.
	(TARGET_DWARF_REGISTER_SPAN): Do not define.
	(TARGET_MEMBER_TYPE_FORCES_BLK): Do not define.
	(invalid_e500_subreg): Delete.
	(rs6000_legitimize_address): Always force_reg op2 as well, for
	paired single memory accesses.
	(rs6000_member_type_forces_blk): Delete.
	(rs6000_spe_function_arg): Delete.
	(rs6000_expand_unop_builtin): Delete SPE handling.
	(rs6000_expand_binop_builtin): Ditto.
	(spe_expand_stv_builtin): Delete.
	(bdesc_2arg_spe): Delete.
	(spe_expand_builtin): Delete.
	(spe_expand_predicate_builtin): Delete.
	(spe_expand_evsel_builtin): Delete.
	(rs6000_invalid_builtin): Remove RS6000_BTM_SPE handling.
	(spe_init_builtins): Delete.
	(spe_func_has_64bit_regs_p): Delete.
	(savres_routine_name): Delete "info" parameter.  Adjust callers.
	(rs6000_emit_stack_reset): Ditto.
	(rs6000_dwarf_register_span): Delete.
	* config/rs6000/rs6000.h (TARGET_SPE_ABI, TARGET_SPE,
	UNITS_PER_SPE_WORD, SPE_HIGH_REGNO_P, SPE_SIMD_REGNO_P,
	SPE_VECTOR_MODE, RS6000_BTM_SPE, RS6000_BUILTIN_E, RS6000_BUILTIN_S):
	Delete.
	* config/rs6000/rs6000.md (FIRST_SPE_HIGH_REGNO, LAST_SPE_HIGH_REGNO):
	Delete.
	* config/rs6000/rs6000.opt (-mabi=spe, -mabi=no-spe): Delete.
	* config/rs6000/spe.md: Delete every pattern that uses TARGET_SPE.
	* config/rs6000/vector.md (absv2sf2, negv2sf2, addv2sf3, subv2sf3,
	mulv2sf3, divv2sf3): Delete expanders.

From-SVN: r248980

gcc/ChangeLog

 2017-06-07  Segher Boessenkool  <segher@kernel.crashing.org>
 
+	* config/rs6000/rs6000-common.c (rs6000_handle_option): Remove
+	SPE ABI handling.
+	* config/rs6000/paired.md (paired_negv2sf2): Rename to negv2sf2.
+	(paired_absv2sf2, paired_addv2sf3, paired_subv2sf3, paired_mulv2sf3,
+	paired_divv2sf3): Similar.
+	* config/rs6000/predicates.md: Replace TARGET_SPE, TARGET_SPE_ABI,
+	SPE_VECTOR_MODE and SPE_HIGH_REGNO_P by 0; simplify.
+	* config/rs6000/rs6000-builtin.def: Delete RS6000_BUILTIN_E and
+	RS6000_BUILTIN_S.
+	Delete BU_SPE_1, BU_SPE_2, BU_SPE_3, BU_SPE_E, BU_SPE_P, and BU_SPE_X.
+	Rename the paired_* instruction patterns.
+	* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Do not
+	define __SPE__.
+	* config/rs6000/rs6000-protos.h (invalid_e500_subreg): Delete.
+	* config/rs6000/rs6000.c: Delete RS6000_BUILTIN_E and RS6000_BUILTIN_S.
+	(struct rs6000_stack): Delete fields spe_gp_save_offset, spe_gp_size,
+	spe_padding_size, and spe_64bit_regs_used.  Replace TARGET_SPE and
+	TARGET_SPE_ABI with 0, simplify.  Replace SPE_VECTOR_MODE with
+	PAIRED_VECTOR_MODE.
+	(struct machine_function): Delete field spe_insn_chain_scanned_p.
+	(spe_func_has_64bit_regs_p): Delete.
+	(spe_expand_predicate_builtin): Delete.
+	(spe_expand_evsel_builtin): Delete.
+	(TARGET_DWARF_REGISTER_SPAN): Do not define.
+	(TARGET_MEMBER_TYPE_FORCES_BLK): Do not define.
+	(invalid_e500_subreg): Delete.
+	(rs6000_legitimize_address): Always force_reg op2 as well, for
+	paired single memory accesses.
+	(rs6000_member_type_forces_blk): Delete.
+	(rs6000_spe_function_arg): Delete.
+	(rs6000_expand_unop_builtin): Delete SPE handling.
+	(rs6000_expand_binop_builtin): Ditto.
+	(spe_expand_stv_builtin): Delete.
+	(bdesc_2arg_spe): Delete.
+	(spe_expand_builtin): Delete.
+	(spe_expand_predicate_builtin): Delete.
+	(spe_expand_evsel_builtin): Delete.
+	(rs6000_invalid_builtin): Remove RS6000_BTM_SPE handling.
+	(spe_init_builtins): Delete.
+	(spe_func_has_64bit_regs_p): Delete.
+	(savres_routine_name): Delete "info" parameter.  Adjust callers.
+	(rs6000_emit_stack_reset): Ditto.
+	(rs6000_dwarf_register_span): Delete.
+	* config/rs6000/rs6000.h (TARGET_SPE_ABI, TARGET_SPE,
+	UNITS_PER_SPE_WORD, SPE_HIGH_REGNO_P, SPE_SIMD_REGNO_P,
+	SPE_VECTOR_MODE, RS6000_BTM_SPE, RS6000_BUILTIN_E, RS6000_BUILTIN_S):
+	Delete.
+	* config/rs6000/rs6000.md (FIRST_SPE_HIGH_REGNO, LAST_SPE_HIGH_REGNO):
+	Delete.
+	* config/rs6000/rs6000.opt (-mabi=spe, -mabi=no-spe): Delete.
+	* config/rs6000/spe.md: Delete every pattern that uses TARGET_SPE.
+	* config/rs6000/vector.md (absv2sf2, negv2sf2, addv2sf3, subv2sf3,
+	mulv2sf3, divv2sf3): Delete expanders.
+
+2017-06-07  Segher Boessenkool  <segher@kernel.crashing.org>
+
 	config/rs6000/rs6000.md (UNSPEC_MV_CR_GT): Delete.
 
 2017-06-07  Segher Boessenkool  <segher@kernel.crashing.org>

gcc/common/config/rs6000/rs6000-common.c

@@ -207,15 +207,6 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
       break;
 #endif
 
-    case OPT_mabi_altivec:
-      /* Enabling the AltiVec ABI turns off the SPE ABI.  */
-      opts->x_rs6000_spe_abi = 0;
-      break;
-
-    case OPT_mabi_spe:
-      opts->x_rs6000_altivec_abi = 0;
-      break;
-
     case OPT_mlong_double_:
       if (value != 64 && value != 128)
 	{

gcc/config/rs6000/paired.md

@@ -26,7 +26,7 @@
    UNSPEC_EXTODD_V2SF
   ])
 
-(define_insn "paired_negv2sf2"
+(define_insn "negv2sf2"
   [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
 	(neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
   "TARGET_PAIRED_FLOAT"
@@ -40,7 +40,7 @@
   "ps_rsqrte %0,%1"
   [(set_attr "type" "fp")])
 
-(define_insn "paired_absv2sf2"
+(define_insn "absv2sf2"
   [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
 	(abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
   "TARGET_PAIRED_FLOAT"
@@ -54,7 +54,7 @@
   "ps_nabs %0,%1"
   [(set_attr "type" "fp")])
 
-(define_insn "paired_addv2sf3"
+(define_insn "addv2sf3"
   [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
 	(plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
 		   (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
@@ -62,7 +62,7 @@
   "ps_add %0,%1,%2"
   [(set_attr "type" "fp")])
 
-(define_insn "paired_subv2sf3"
+(define_insn "subv2sf3"
   [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
         (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
                     (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
@@ -70,7 +70,7 @@
   "ps_sub %0,%1,%2"
   [(set_attr "type" "fp")])
 
-(define_insn "paired_mulv2sf3"
+(define_insn "mulv2sf3"
   [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
 	(mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
 		   (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
@@ -85,7 +85,7 @@
   "ps_res %0,%1"
   [(set_attr "type" "fp")])
 
-(define_insn "paired_divv2sf3"
+(define_insn "divv2sf3"
   [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
 	(div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
 		  (match_operand:V2SF 2 "gpc_reg_operand" "f")))]

gcc/config/rs6000/predicates.md

@@ -299,9 +299,6 @@
 (define_predicate "gpc_reg_operand"
   (match_operand 0 "register_operand")
 {
-  if (TARGET_SPE && invalid_e500_subreg (op, mode))
-    return 0;
-
   if (GET_CODE (op) == SUBREG)
     {
       if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
@@ -331,9 +328,6 @@
 (define_predicate "int_reg_operand"
   (match_operand 0 "register_operand")
 {
-  if (TARGET_SPE && invalid_e500_subreg (op, mode))
-    return 0;
-
   if (GET_CODE (op) == SUBREG)
     {
       if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
@@ -357,9 +351,6 @@
 (define_predicate "int_reg_operand_not_pseudo"
   (match_operand 0 "register_operand")
 {
-  if (TARGET_SPE && invalid_e500_subreg (op, mode))
-    return 0;
-
   if (GET_CODE (op) == SUBREG)
     op = SUBREG_REG (op);
 
@@ -711,32 +702,6 @@
       return easy_altivec_constant (op, mode);
     }
 
-  if (SPE_VECTOR_MODE (mode))
-    {
-      int cst, cst2;
-      if (zero_constant (op, mode))
-	return true;
-      if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
-        return false;
-
-      /* Limit SPE vectors to 15 bits signed.  These we can generate with:
-	   li r0, CONSTANT1
-	   evmergelo r0, r0, r0
-	   li r0, CONSTANT2
-
-	 I don't know how efficient it would be to allow bigger constants,
-	 considering we'll have an extra 'ori' for every 'li'.  I doubt 5
-	 instructions is better than a 64-bit memory load, but I don't
-	 have the e500 timing specs.  */
-      if (mode == V2SImode)
-	{
-	  cst  = INTVAL (CONST_VECTOR_ELT (op, 0));
-	  cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
-	  return cst  >= -0x7fff && cst <= 0x7fff
-	         && cst2 >= -0x7fff && cst2 <= 0x7fff;
-	}
-    }
-
   return false;
 })
 
@@ -1135,12 +1100,6 @@
       && easy_vector_constant (op, mode))
     return 1;
 
-  /* Do not allow invalid E500 subregs.  */
-  if (TARGET_SPE
-      && GET_CODE (op) == SUBREG
-      && invalid_e500_subreg (op, mode))
-    return 0;
-
   /* For floating-point or multi-word mode, the only remaining valid type
      is a register.  */
   if (SCALAR_FLOAT_MODE_P (mode)
@@ -1199,16 +1158,10 @@
   return gpc_reg_operand (op, mode);
 })
 
-;; Return true if OP is a non-immediate operand and not an invalid
-;; SUBREG operation on the e500.
+;; Return true if OP is a non-immediate operand.
 (define_predicate "rs6000_nonimmediate_operand"
   (match_code "reg,subreg,mem")
 {
-  if (TARGET_SPE
-      && GET_CODE (op) == SUBREG
-      && invalid_e500_subreg (op, mode))
-    return 0;
-
   return nonimmediate_operand (op, mode);
 })
 

gcc/config/rs6000/rs6000-c.c

@@ -611,10 +611,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
     rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_SF__");
 
   /* options from the builtin masks.  */
-  /* Note that RS6000_BTM_SPE is enabled only if TARGET_SPE
-     (e.g. -mspe).  */
-  if ((bu_mask & RS6000_BTM_SPE) != 0)
-    rs6000_define_or_undefine_macro (define_p, "__SPE__");
   /* Note that RS6000_BTM_PAIRED is enabled only if
      TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired).  */
   if ((bu_mask & RS6000_BTM_PAIRED) != 0)

gcc/config/rs6000/rs6000-protos.h

@@ -41,7 +41,6 @@ extern int small_data_operand (rtx, machine_mode);
 extern bool mem_operand_gpr (rtx, machine_mode);
 extern bool mem_operand_ds_form (rtx, machine_mode);
 extern bool toc_relative_expr_p (const_rtx, bool);
-extern bool invalid_e500_subreg (rtx, machine_mode);
 extern void validate_condition_mode (enum rtx_code, machine_mode);
 extern bool legitimate_constant_pool_address_p (const_rtx, machine_mode,
 						bool);

gcc/config/rs6000/rs6000.h

@@ -569,8 +569,6 @@ extern int rs6000_vector_align[];
 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
 
-#define TARGET_SPE_ABI 0
-#define TARGET_SPE 0
 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
 
 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
@@ -704,7 +702,7 @@ extern int rs6000_vector_align[];
    the compiler for those builtins, and those machines don't support altivec or
    VSX.  */
 
-#define TARGET_EXTRA_BUILTINS	(!TARGET_SPE && !TARGET_PAIRED_FLOAT	 \
+#define TARGET_EXTRA_BUILTINS	(!TARGET_PAIRED_FLOAT			 \
 				 && ((TARGET_POWERPC64			 \
 				      || TARGET_PPC_GPOPT /* 970/power4 */ \
 				      || TARGET_POPCNTB	  /* ISA 2.02 */ \
@@ -869,7 +867,6 @@ extern unsigned char rs6000_recip_bits[];
 #define UNITS_PER_FP_WORD 8
 #define UNITS_PER_ALTIVEC_WORD 16
 #define UNITS_PER_VSX_WORD 16
-#define UNITS_PER_SPE_WORD 8
 #define UNITS_PER_PAIRED_WORD 8
 
 /* Type used for ptrdiff_t, as a string used in a declaration.  */
@@ -971,8 +968,7 @@ enum data_align { align_abi, align_opt, align_both };
 #define DATA_ALIGNMENT(TYPE, ALIGN) \
   rs6000_data_alignment (TYPE, ALIGN, align_opt)
 
-/* Align vectors to 128 bits.  Align SPE vectors and E500 v2 doubles to
-   64 bits.  */
+/* Align vectors to 128 bits.  */
 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
   rs6000_data_alignment (TYPE, ALIGN, align_abi)
 
@@ -983,9 +979,8 @@ enum data_align { align_abi, align_opt, align_both };
 /* Define this macro to be the value 1 if unaligned accesses have a cost
    many times greater than aligned accesses, for example if they are
    emulated in a trap handler.  */
-/* Altivec vector memory instructions simply ignore the low bits; SPE vector
-   memory instructions trap on unaligned accesses; VSX memory instructions are
-   aligned to 4 or 8 bytes.  */
+/* Altivec vector memory instructions simply ignore the low bits; VSX memory
+   instructions are aligned to 4 or 8 bytes.  */
 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN)				\
   (STRICT_ALIGNMENT							\
    || (!TARGET_EFFICIENT_UNALIGNED_VSX					\
@@ -1027,12 +1022,7 @@ enum data_align { align_abi, align_opt, align_both };
 /* This must be included for pre gcc 3.0 glibc compatibility.  */
 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
 
-/* True if register is an SPE High register.  */
-#define SPE_HIGH_REGNO_P(N) \
-  ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO)
-
-/* SPE high registers added as hard regs.
-   The sfp register and 3 HTM registers
+/* The sfp register and 3 HTM registers
    aren't included in DWARF_FRAME_REGISTERS.  */
 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
 
@@ -1227,9 +1217,6 @@ enum data_align { align_abi, align_opt, align_both };
 #define INT_REGNO_P(N) \
   ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
 
-/* SPE SIMD registers are just the GPRs.  */
-#define SPE_SIMD_REGNO_P(N) ((N) <= 31)
-
 /* PAIRED SIMD registers are just the FPRs.  */
 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
 
@@ -1305,12 +1292,6 @@ enum data_align { align_abi, align_opt, align_both };
   (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE)			\
    || (MODE) == V2DImode || (MODE) == V1TImode)
 
-#define SPE_VECTOR_MODE(MODE)		\
-	((MODE) == V4HImode          	\
-         || (MODE) == V2SFmode          \
-         || (MODE) == V1DImode          \
-         || (MODE) == V2SImode)
-
 #define PAIRED_VECTOR_MODE(MODE)        \
          ((MODE) == V2SFmode)            
 
@@ -1347,9 +1328,9 @@ enum data_align { align_abi, align_opt, align_both };
    ? GET_MODE_CLASS (MODE2) == MODE_CC		\
    : GET_MODE_CLASS (MODE2) == MODE_CC		\
    ? 0						\
-   : SPE_VECTOR_MODE (MODE1)			\
-   ? SPE_VECTOR_MODE (MODE2)			\
-   : SPE_VECTOR_MODE (MODE2)			\
+   : PAIRED_VECTOR_MODE (MODE1)			\
+   ? PAIRED_VECTOR_MODE (MODE2)			\
+   : PAIRED_VECTOR_MODE (MODE2)			\
    ? 0						\
    : 1)
 
@@ -2684,7 +2665,7 @@ extern int frame_pointer_needed;
 #define RS6000_BTC_SAT		RS6000_BTC_MISC	/* saturate sets VSCR.  */
 
 /* Builtin targets.  For now, we reuse the masks for those options that are in
-   target flags, and pick three random bits for SPE, paired and ldbl128 which
+   target flags, and pick two random bits for paired and ldbl128, which
    aren't in target_flags.  */
 #define RS6000_BTM_ALWAYS	0		/* Always enabled.  */
 #define RS6000_BTM_ALTIVEC	MASK_ALTIVEC	/* VMX/altivec vectors.  */
@@ -2695,7 +2676,6 @@ extern int frame_pointer_needed;
 #define RS6000_BTM_P9_MISC	MASK_P9_MISC	/* ISA 3.0 misc. non-vector */
 #define RS6000_BTM_CRYPTO	MASK_CRYPTO	/* crypto funcs.  */
 #define RS6000_BTM_HTM		MASK_HTM	/* hardware TM funcs.  */
-#define RS6000_BTM_SPE		MASK_STRING	/* E500 */
 #define RS6000_BTM_PAIRED	MASK_MULHW	/* 750CL paired insns.  */
 #define RS6000_BTM_FRE		MASK_POPCNTB	/* FRE instruction.  */
 #define RS6000_BTM_FRES		MASK_PPC_GFXOPT	/* FRES instruction.  */
@@ -2736,11 +2716,9 @@ extern int frame_pointer_needed;
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
 #undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
 #undef RS6000_BUILTIN_X
 
 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
@@ -2749,11 +2727,9 @@ extern int frame_pointer_needed;
 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
 
 enum rs6000_builtins
@@ -2769,11 +2745,9 @@ enum rs6000_builtins
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
 #undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
 #undef RS6000_BUILTIN_X
 
 enum rs6000_builtin_type_index

gcc/config/rs6000/rs6000.md

@@ -56,8 +56,6 @@
    (TFHAR_REGNO			114)
    (TFIAR_REGNO			115)
    (TEXASR_REGNO		116)
-   (FIRST_SPE_HIGH_REGNO	117)
-   (LAST_SPE_HIGH_REGNO		148)
   ])
 
 ;;

gcc/config/rs6000/rs6000.opt

@@ -381,14 +381,6 @@ mabi=no-altivec
 Target RejectNegative Var(rs6000_altivec_abi, 0)
 Do not use the AltiVec ABI extensions.
 
-mabi=spe
-Target RejectNegative Var(rs6000_spe_abi) Save
-Use the SPE ABI extensions.
-
-mabi=no-spe
-Target RejectNegative Var(rs6000_spe_abi, 0)
-Do not use the SPE ABI extensions.
-
 mabi=elfv1
 Target RejectNegative Var(rs6000_elf_abi, 1) Save
 Use the ELFv1 ABI.

gcc/config/rs6000/vector.md

@@ -1309,98 +1309,3 @@
     emit_insn (gen_vsx_extract_<VEC_F:mode> (operand0, vec, elt));
     DONE;
   })
-
-
-;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems.
-
-(define_expand "absv2sf2"
-  [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
-	(abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
-  "TARGET_PAIRED_FLOAT || TARGET_SPE"
-  "")
-
-(define_expand "negv2sf2"
-  [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
-	(neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
-  "TARGET_PAIRED_FLOAT || TARGET_SPE"
-  "")
-
-(define_expand "addv2sf3"
-  [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
-	(plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
-		   (match_operand:V2SF 2 "gpc_reg_operand" "")))]
-  "TARGET_PAIRED_FLOAT || TARGET_SPE"
-  "
-{
-  if (TARGET_SPE)
-    {
-      /* We need to make a note that we clobber SPEFSCR.  */
-      rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
-
-      XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
-                                         gen_rtx_PLUS (V2SFmode, operands[1], operands[2]));
-      XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
-      emit_insn (par);
-      DONE;
-    }
-}")
-
-(define_expand "subv2sf3"
-  [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
-	(minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
-		    (match_operand:V2SF 2 "gpc_reg_operand" "")))]
-  "TARGET_PAIRED_FLOAT || TARGET_SPE"
-  "
-{
-  if (TARGET_SPE)
-    {
-      /* We need to make a note that we clobber SPEFSCR.  */
-      rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
-
-      XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
-                                         gen_rtx_MINUS (V2SFmode, operands[1], operands[2]));
-      XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
-      emit_insn (par);
-      DONE;
-    }
-}")
-
-(define_expand "mulv2sf3"
-  [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
-	(mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
-		   (match_operand:V2SF 2 "gpc_reg_operand" "")))]
-  "TARGET_PAIRED_FLOAT || TARGET_SPE"
-  "
-{
-  if (TARGET_SPE)
-    {
-      /* We need to make a note that we clobber SPEFSCR.  */
-      rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
-
-      XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
-                                         gen_rtx_MULT (V2SFmode, operands[1], operands[2]));
-      XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
-      emit_insn (par);
-      DONE;
-    }
-}")
-
-(define_expand "divv2sf3"
-  [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
-	(div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
-		  (match_operand:V2SF 2 "gpc_reg_operand" "")))]
-  "TARGET_PAIRED_FLOAT || TARGET_SPE"
-  "
-{
-  if (TARGET_SPE)
-    {
-      /* We need to make a note that we clobber SPEFSCR.  */
-      rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
-
-      XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
-                                         gen_rtx_DIV (V2SFmode, operands[1], operands[2]));
-      XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
-      emit_insn (par);
-      DONE;
-    }
-}")