Use more conservative fences on RISC-V

The RISC-V memory model is still in the process of being formally
specified, so for now we're going to be safe and add the I/O bits to
userspace fences because there's no way to know if userspace is touching
memory-mapped I/O regions at compile time.

This will have no impact on existing microarchitecutres because they
treat all fences conservatively.

gcc/ChangeLog:

2017-03-17  Palmer Dabbelt  <palmer@dabbelt.com>

        * config/riscv/riscv.c (riscv_print_operand): Use "fence
        iorw,ow".
        * config/riscv/sync.mc (mem_thread_fence_1): Use "fence
        iorw,iorw".

From-SVN: r246282

gcc/ChangeLog

+2017-03-17  Palmer Dabbelt  <palmer@dabbelt.com>
+
+	* config/riscv/riscv.c (riscv_print_operand): Use "fence
+	iorw,ow".
+	* config/riscv/sync.mc (mem_thread_fence_1): Use "fence
+	iorw,iorw".
+
 2017-03-20  Marek Polacek  <polacek@redhat.com>
 
 	PR sanitizer/80063

gcc/config/riscv/riscv.c

@@ -2794,7 +2794,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)
 
     case 'F':
       if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op)))
-	fputs ("fence rw,w; ", file);
+	fputs ("fence iorw,ow; ", file);
       break;
 
     default:

gcc/config/riscv/sync.md

@@ -53,7 +53,7 @@
 	(unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
    (match_operand:SI 1 "const_int_operand" "")] ;; model
   ""
-  "fence\trw,rw")
+  "fence\tiorw,iorw")
 
 ;; Atomic memory operations.