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Commit e04108c7 by Claudiu Zissulescu Committed by Claudiu Zissulescu
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[ARC] Avoid specific constants to end in limm field. 

Avoid constants to end up in the limm field for particular
instructions when compiling for size.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (*add_n): Clean up pattern, update instruction
	constraints.
	(ashlsi3_insn): Update instruction constraints.
	(ashrsi3_insn): Likewise.
	(rotrsi3): Likewise.
	(add_shift): Likewise.
	* config/arc/constraints.md (Csz): New 32 bit constraint. It
	avoids placing in the limm field small constants which, otherwise,
	could end into a small instruction.

testsuite/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/tph_addx.c: New test.

From-SVN: r264737
parent 97e1d32c
Showing with 93 additions and 31 deletions
gcc/ChangeLog
2018-10-01 Claudiu Zissulescu <claziss@synopsys.com> 2018-10-01 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (*add_n): Clean up pattern, update instruction
constraints.
(ashlsi3_insn): Update instruction constraints.
(ashrsi3_insn): Likewise.
(rotrsi3): Likewise.
(add_shift): Likewise.
* config/arc/constraints.md (Csz): New 32 bit constraint. It
avoids placing in the limm field small constants which, otherwise,
could end into a small instruction.
2018-10-01 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (maddsidi4_split): Don't use dmac if the * config/arc/arc.md (maddsidi4_split): Don't use dmac if the
destination register is not odd-even. destination register is not odd-even.
(umaddsidi4_split): Likewise. (umaddsidi4_split): Likewise.
......
gcc/config/arc/arc.md
...@@ -3173,30 +3173,17 @@ archs4x, archs4xd, archs4xd_slow" ...@@ -3173,30 +3173,17 @@ archs4x, archs4xd, archs4xd_slow"
(set (match_dup 3) (match_dup 4))]) (set (match_dup 3) (match_dup 4))])
(define_insn "*add_n" (define_insn "*add_n"
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcw,W,W,w,w") [(set (match_operand:SI 0 "dest_reg_operand" "=q,r,r")
(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "Rcqq,c,c,c,c,c") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "q,r,r")
(match_operand:SI 2 "_1_2_3_operand" ""))
(match_operand:SI 3 "nonmemory_operand" "0,0,c,?Cal,?c,??Cal")))]
""
"add%c2%? %0,%3,%1%&"
[(set_attr "type" "shift")
(set_attr "length" "*,4,4,8,4,8")
(set_attr "predicable" "yes,yes,no,no,no,no")
(set_attr "cond" "canuse,canuse,nocond,nocond,nocond,nocond")
(set_attr "iscompact" "maybe,false,false,false,false,false")])
(define_insn "*add_n"
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcw,W,W,w,w")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "Rcqq,c,c,c,c,c")
(match_operand:SI 2 "_2_4_8_operand" "")) (match_operand:SI 2 "_2_4_8_operand" ""))
(match_operand:SI 3 "nonmemory_operand" "0,0,c,?Cal,?c,??Cal")))] (match_operand:SI 3 "nonmemory_operand" "0,r,Csz")))]
"" ""
"add%z2%? %0,%3,%1%&" "add%z2%?\\t%0,%3,%1%&"
[(set_attr "type" "shift") [(set_attr "type" "shift")
(set_attr "length" "*,4,4,8,4,8") (set_attr "length" "*,4,8")
(set_attr "predicable" "yes,yes,no,no,no,no") (set_attr "predicable" "yes,no,no")
(set_attr "cond" "canuse,canuse,nocond,nocond,nocond,nocond") (set_attr "cond" "canuse,nocond,nocond")
(set_attr "iscompact" "maybe,false,false,false,false,false")]) (set_attr "iscompact" "maybe,false,false")])
;; N.B. sub[123] has the operands of the MINUS in the opposite order from ;; N.B. sub[123] has the operands of the MINUS in the opposite order from
;; what synth_mult likes. ;; what synth_mult likes.
...@@ -3613,7 +3600,7 @@ archs4x, archs4xd, archs4xd_slow" ...@@ -3613,7 +3600,7 @@ archs4x, archs4xd, archs4xd_slow"
; provide one alternatice for this, without condexec support. ; provide one alternatice for this, without condexec support.
(define_insn "*ashlsi3_insn" (define_insn "*ashlsi3_insn"
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w") [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w")
(ashift:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCal") (ashift:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCsz")
(match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))] (match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))]
"TARGET_BARREL_SHIFTER "TARGET_BARREL_SHIFTER
&& (register_operand (operands[1], SImode) && (register_operand (operands[1], SImode)
...@@ -3626,7 +3613,7 @@ archs4x, archs4xd, archs4xd_slow" ...@@ -3626,7 +3613,7 @@ archs4x, archs4xd, archs4xd_slow"
(define_insn "*ashrsi3_insn" (define_insn "*ashrsi3_insn"
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w") [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w")
(ashiftrt:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCal") (ashiftrt:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCsz")
(match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))] (match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))]
"TARGET_BARREL_SHIFTER "TARGET_BARREL_SHIFTER
&& (register_operand (operands[1], SImode) && (register_operand (operands[1], SImode)
...@@ -3653,7 +3640,7 @@ archs4x, archs4xd, archs4xd_slow" ...@@ -3653,7 +3640,7 @@ archs4x, archs4xd, archs4xd_slow"
(define_insn "rotrsi3" (define_insn "rotrsi3"
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcw, w, w") [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw, w, w")
(rotatert:SI (match_operand:SI 1 "register_operand" " 0,cL,cCal") (rotatert:SI (match_operand:SI 1 "register_operand" " 0,cL,cCsz")
(match_operand:SI 2 "nonmemory_operand" "cL,cL,cCal")))] (match_operand:SI 2 "nonmemory_operand" "cL,cL,cCal")))]
"TARGET_BARREL_SHIFTER" "TARGET_BARREL_SHIFTER"
"ror%? %0,%1,%2" "ror%? %0,%1,%2"
...@@ -4494,16 +4481,16 @@ archs4x, archs4xd, archs4xd_slow" ...@@ -4494,16 +4481,16 @@ archs4x, archs4xd, archs4xd_slow"
(define_peephole2 (define_peephole2
[(set (match_operand:SI 0 "dest_reg_operand" "") [(set (match_operand:SI 0 "dest_reg_operand" "")
(ashift:SI (match_operand:SI 1 "register_operand" "") (ashift:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" ""))) (match_operand:SI 2 "_1_2_3_operand" "")))
(set (match_operand:SI 3 "dest_reg_operand" "") (set (match_operand:SI 3 "dest_reg_operand" "")
(plus:SI (match_operand:SI 4 "nonmemory_operand" "") (plus:SI (match_operand:SI 4 "nonmemory_operand" "")
(match_operand:SI 5 "nonmemory_operand" "")))] (match_operand:SI 5 "nonmemory_operand" "")))]
"(INTVAL (operands[2]) == 1 "(true_regnum (operands[4]) == true_regnum (operands[0])
|| INTVAL (operands[2]) == 2
|| INTVAL (operands[2]) == 3)
&& (true_regnum (operands[4]) == true_regnum (operands[0])
|| true_regnum (operands[5]) == true_regnum (operands[0])) || true_regnum (operands[5]) == true_regnum (operands[0]))
&& (peep2_reg_dead_p (2, operands[0]) || (true_regnum (operands[3]) == true_regnum (operands[0])))" && (peep2_reg_dead_p (2, operands[0])
|| (true_regnum (operands[3]) == true_regnum (operands[0])))
&& !(optimize_size && satisfies_constraint_I (operands[4]))
&& !(optimize_size && satisfies_constraint_I (operands[5]))"
;; the preparation statements take care to put proper operand in operands[4] ;; the preparation statements take care to put proper operand in operands[4]
;; operands[4] will always contain the correct operand. This is added to satisfy commutativity ;; operands[4] will always contain the correct operand. This is added to satisfy commutativity
[(set (match_dup 3) [(set (match_dup 3)
...@@ -6560,7 +6547,7 @@ archs4x, archs4xd, archs4xd_slow" ...@@ -6560,7 +6547,7 @@ archs4x, archs4xd, archs4xd_slow"
[(set (match_operand:SI 0 "register_operand" "=q,r,r") [(set (match_operand:SI 0 "register_operand" "=q,r,r")
(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "q,r,r") (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "q,r,r")
(match_operand:SI 2 "_1_2_3_operand" "")) (match_operand:SI 2 "_1_2_3_operand" ""))
(match_operand:SI 3 "nonmemory_operand" "0,r,Cal")))] (match_operand:SI 3 "nonmemory_operand" "0,r,Csz")))]
"" ""
"add%2%?\\t%0,%3,%1" "add%2%?\\t%0,%3,%1"
[(set_attr "length" "*,4,8") [(set_attr "length" "*,4,8")
......
gcc/config/arc/constraints.md
...@@ -435,6 +435,12 @@ ...@@ -435,6 +435,12 @@
&& !arc_legitimate_pic_addr_p (op) && !arc_legitimate_pic_addr_p (op)
&& !satisfies_constraint_I (op)")) && !satisfies_constraint_I (op)"))
(define_constraint "Csz"
"a 32 bit constant avoided when compiling for size."
(match_test "immediate_operand (op, VOIDmode)
&& !arc_legitimate_pic_addr_p (op)
&& !(satisfies_constraint_I (op) && optimize_size)"))
; Note that the 'cryptic' register constraints will not make reload use the ; Note that the 'cryptic' register constraints will not make reload use the
; associated class to reload into, but this will not penalize reloading of any ; associated class to reload into, but this will not penalize reloading of any
; other operands, or using an alternate part of the same alternative. ; other operands, or using an alternate part of the same alternative.
......
gcc/testsuite/ChangeLog
2018-10-01 Claudiu Zissulescu <claziss@synopsys.com> 2018-10-01 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/tph_addx.c: New test.
2018-10-01 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/tmac-3.c: New file. * gcc.target/arc/tmac-3.c: New file.
2018-09-30 Paul Thomas <pault@gcc.gnu.org> 2018-09-30 Paul Thomas <pault@gcc.gnu.org>
......
gcc/testsuite/gcc.target/arc/tph_addx.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-Os" } */
/* when compiling for size avoid the following peephole
-------------------------------------------------------------
Pattern 1 : r0 = r1 << {i}
r3 = r4/INT + r0 ;;and commutative
||
\/
add{i} r3,r4/INT,r1
-------------------------------------------------------------
*/
typedef int a;
typedef int b ;
struct c
{
b d;
};
struct e
{
a f;
};
int g(int family)
{
switch (family)
case 2:
return sizeof(struct e);
return 0;
}
int h(int family)
{
return 1 + g(family) - 1 ;
}
extern void m (void);
int i(int j)
{
struct c *hdr;
int k;
int l;
k = h(j);
l = sizeof(struct c) + k * 2;
hdr->d = l ;
if (j)
m();
}
/* { dg-final { scan-assembler-not "add\d" } } */
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