arm.md (split for extendsidi): Update condition.

2013-02-22  Greta Yorsh  <Greta.Yorsh@arm.com>

        * config/arm/arm.md (split for extendsidi): Update condition.
        (zero_extend<mode>di2,extend<mode>di2): Add an alternative.
        * config/arm/iterators.md (qhs_extenddi_cstr): Likewise.
        (qhs_zextenddi_cstr): Likewise.

From-SVN: r196220

gcc/ChangeLog

+2013-02-22  Greta Yorsh  <Greta.Yorsh@arm.com>
+
+        * config/arm/arm.md (split for extendsidi): Update condition.
+        (zero_extend<mode>di2,extend<mode>di2): Add an alternative.
+        * config/arm/iterators.md (qhs_extenddi_cstr): Likewise.
+        (qhs_zextenddi_cstr): Likewise.
+
 2013-02-21  Jakub Jelinek  <jakub@redhat.com>
 
 	PR middle-end/56420

gcc/config/arm/arm.md

@@ -4492,36 +4492,35 @@
 ;; Zero and sign extension instructions.
 
 (define_insn "zero_extend<mode>di2"
-  [(set (match_operand:DI 0 "s_register_operand" "=w,r,?r")
+  [(set (match_operand:DI 0 "s_register_operand" "=w,r,?r,w")
         (zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>"
 					    "<qhs_zextenddi_cstr>")))]
   "TARGET_32BIT <qhs_zextenddi_cond>"
   "#"
-  [(set_attr "length" "8,4,8")
+  [(set_attr "length" "8,4,8,8")
+   (set_attr "arch" "neon_nota8,*,*,neon_onlya8")
    (set_attr "ce_count" "2")
    (set_attr "predicable" "yes")]
 )
 
 (define_insn "extend<mode>di2"
-  [(set (match_operand:DI 0 "s_register_operand" "=w,r,?r,?r")
+  [(set (match_operand:DI 0 "s_register_operand" "=w,r,?r,?r,w")
         (sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
 					    "<qhs_extenddi_cstr>")))]
   "TARGET_32BIT <qhs_sextenddi_cond>"
   "#"
-  [(set_attr "length" "8,4,8,8")
+  [(set_attr "length" "8,4,8,8,8")
    (set_attr "ce_count" "2")
    (set_attr "shift" "1")
    (set_attr "predicable" "yes")
-   (set_attr "arch" "*,*,a,t")]
+   (set_attr "arch" "neon_nota8,*,a,t,neon_onlya8")]
 )
 
 ;; Splits for all extensions to DImode
 (define_split
   [(set (match_operand:DI 0 "s_register_operand" "")
         (zero_extend:DI (match_operand 1 "nonimmediate_operand" "")))]
-  "TARGET_32BIT && (!TARGET_NEON
-		    || (reload_completed
-			&& !(IS_VFP_REGNUM (REGNO (operands[0])))))"
+  "TARGET_32BIT && reload_completed && !IS_VFP_REGNUM (REGNO (operands[0]))"
   [(set (match_dup 0) (match_dup 1))]
 {
   rtx lo_part = gen_lowpart (SImode, operands[0]);
@@ -4547,9 +4546,7 @@
 (define_split
   [(set (match_operand:DI 0 "s_register_operand" "")
         (sign_extend:DI (match_operand 1 "nonimmediate_operand" "")))]
-  "TARGET_32BIT && (!TARGET_NEON
-		    || (reload_completed
-			&& !(IS_VFP_REGNUM (REGNO (operands[0])))))"
+  "TARGET_32BIT && reload_completed && !IS_VFP_REGNUM (REGNO (operands[0]))"
   [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
 {
   rtx lo_part = gen_lowpart (SImode, operands[0]);

gcc/config/arm/iterators.md

@@ -429,8 +429,8 @@
 (define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
 				   (HI "nonimmediate_operand")
 				   (QI "arm_reg_or_extendqisi_mem_op")])
-(define_mode_attr qhs_extenddi_cstr [(SI "r,0,r,r") (HI "r,0,rm,rm") (QI "r,0,rUq,rm")])
-(define_mode_attr qhs_zextenddi_cstr [(SI "r,0,r") (HI "r,0,rm") (QI "r,0,rm")])
+(define_mode_attr qhs_extenddi_cstr [(SI "r,0,r,r,r") (HI "r,0,rm,rm,r") (QI "r,0,rUq,rm,r")])
+(define_mode_attr qhs_zextenddi_cstr [(SI "r,0,r,r") (HI "r,0,rm,r") (QI "r,0,rm,r")])
 
 ;; Mode attributes used for fixed-point support.
 (define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16")