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riscv-gcc-1
Commit dfa08768 by Richard Earnshaw Committed by Richard Earnshaw
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Delete target options -m2 -m3 & -m6. 

Fix pic register initialization.
Update zero-extraction patterns.

From-SVN: r25435
parent bd505538
Showing with 52 additions and 68 deletions
gcc/ChangeLog
Thu Feb 25 10:44:35 1999 Richard Earnshaw (rearnsha@arm.com)
* arm.h (TARGET_SWITCHES): Delete deprecated switches -m[236].
(TARGET_3, TARGET_6): Delete.
(ARM_FLAG_ARM[36]): Delete.
(CPP_CPU_ARCH_SPEC): No need to handle -m[236] any more.
(CC1_SPEC): Don't expand -m[236] into new equivalents.
(CPP_APCS_PC_SPEC): No need to handle -m[236] any more.
* arm.c (arm_override_options): Delete warnings about deprecated
options -m[236].
* arm.c (arm_finalize_pic): Build the label into the special pic
adjustment insn instead of issuing it separately.
* arm.md (pic_add_dot_plus_eight): Rework to contain the label
that is needed.
* arm.md (*zeroextractqi_compare0_scratch): Delete.
(*ne_zeroextractsi): New pattern.
Thu Feb 25 18:40:06 1999 J"orn Rennecke <amylaar@cygnus.co.uk> Thu Feb 25 18:40:06 1999 J"orn Rennecke <amylaar@cygnus.co.uk>
* stmt.c (expand_end_loop): Grok code emitted by * stmt.c (expand_end_loop): Grok code emitted by
......
gcc/config/arm/arm.c
...@@ -356,19 +356,6 @@ arm_override_options () ...@@ -356,19 +356,6 @@ arm_override_options ()
} }
} }
/* Cope with some redundant flags. */
if (TARGET_6)
{
warning ("Option '-m6' deprecated. Use: '-mapcs-32' or -mcpu=<proc>");
target_flags |= ARM_FLAG_APCS_32;
}
if (TARGET_3)
{
warning ("Option '-m3' deprecated. Use: '-mapcs-26' or -mcpu=<proc>");
target_flags &= ~ARM_FLAG_APCS_32;
}
/* Make sure that the processor choice does not conflict with any of the /* Make sure that the processor choice does not conflict with any of the
other command line choices. */ other command line choices. */
if (TARGET_APCS_32 && !(flags & FL_MODE32)) if (TARGET_APCS_32 && !(flags & FL_MODE32))
...@@ -1490,18 +1477,16 @@ arm_finalize_pic () ...@@ -1490,18 +1477,16 @@ arm_finalize_pic ()
l1 = gen_label_rtx (); l1 = gen_label_rtx ();
global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
/* The PC contains 'dot'+8, but the label L1 is on the next /* On the ARM the PC register contains 'dot + 8' at the time of the
instruction, so the offset is only 'dot'+4. */ addition. */
pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), 8);
GEN_INT (4));
pic_tmp2 = gen_rtx_CONST (VOIDmode, pic_tmp2 = gen_rtx_CONST (VOIDmode,
gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx)); gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp)); pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx)); emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));
emit_jump_insn (gen_pic_add_dot_plus_eight(l1, pic_offset_table_rtx)); emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
emit_label (l1);
seq = gen_sequence (); seq = gen_sequence ();
end_sequence (); end_sequence ();
......
gcc/config/arm/arm.h
...@@ -122,9 +122,6 @@ Unrecognized value in TARGET_CPU_DEFAULT. ...@@ -122,9 +122,6 @@ Unrecognized value in TARGET_CPU_DEFAULT.
/* Set the architecture define -- if -march= is set, then it overrides /* Set the architecture define -- if -march= is set, then it overrides
the -mcpu= setting. */ the -mcpu= setting. */
#define CPP_CPU_ARCH_SPEC "\ #define CPP_CPU_ARCH_SPEC "\
%{m2:-D__arm2__ -D__ARM_ARCH_2__} \
%{m3:-D__arm2__ -D__ARM_ARCH_2__} \
%{m6:-D__arm6__ -D__ARM_ARCH_3__} \
%{march=arm2:-D__ARM_ARCH_2__} \ %{march=arm2:-D__ARM_ARCH_2__} \
%{march=arm250:-D__ARM_ARCH_2__} \ %{march=arm250:-D__ARM_ARCH_2__} \
%{march=arm3:-D__ARM_ARCH_2__} \ %{march=arm3:-D__ARM_ARCH_2__} \
...@@ -178,18 +175,15 @@ Unrecognized value in TARGET_CPU_DEFAULT. ...@@ -178,18 +175,15 @@ Unrecognized value in TARGET_CPU_DEFAULT.
%{mcpu=strongarm:-D__ARM_ARCH_4__} \ %{mcpu=strongarm:-D__ARM_ARCH_4__} \
%{mcpu=strongarm110:-D__ARM_ARCH_4__} \ %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
%{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
%{!mcpu*:%{!m6:%{!m2:%{!m3:%(cpp_cpu_arch_default)}}}}} \ %{!mcpu*:%(cpp_cpu_arch_default)}} \
" "
/* Define __APCS_26__ if the PC also contains the PSR */ /* Define __APCS_26__ if the PC also contains the PSR */
/* This also examines deprecated -m[236] if neither of -mapcs-{26,32} is set,
??? Delete this for 2.9. */
#define CPP_APCS_PC_SPEC "\ #define CPP_APCS_PC_SPEC "\
%{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \ %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
-D__APCS_32__} \ -D__APCS_32__} \
%{mapcs-26:-D__APCS_26__} \ %{mapcs-26:-D__APCS_26__} \
%{!mapcs-32: %{!mapcs-26:%{m6:-D__APCS_32__} %{m2:-D__APCS_26__} \ %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
%{m3:-D__APCS_26__} %{!m6:%{!m3:%{!m2:%(cpp_apcs_pc_default)}}}}} \
" "
#ifndef CPP_APCS_PC_DEFAULT_SPEC #ifndef CPP_APCS_PC_DEFAULT_SPEC
...@@ -217,14 +211,7 @@ Unrecognized value in TARGET_CPU_DEFAULT. ...@@ -217,14 +211,7 @@ Unrecognized value in TARGET_CPU_DEFAULT.
/* Default is little endian, which doesn't define anything. */ /* Default is little endian, which doesn't define anything. */
#define CPP_ENDIAN_DEFAULT_SPEC "" #define CPP_ENDIAN_DEFAULT_SPEC ""
/* Translate (for now) the old -m[236] option into the appropriate -mcpu=... #define CC1_SPEC ""
and -mapcs-xx equivalents.
??? Remove support for this style in 2.9.*/
#define CC1_SPEC "\
%{m2:-mcpu=arm2 -mapcs-26} \
%{m3:-mcpu=arm3 -mapcs-26} \
%{m6:-mcpu=arm6 -mapcs-32} \
"
/* This macro defines names of additional specifications to put in the specs /* This macro defines names of additional specifications to put in the specs
that can be used in various specifications like CC1_SPEC. Its definition that can be used in various specifications like CC1_SPEC. Its definition
...@@ -278,19 +265,13 @@ extern char * target_fp_name; ...@@ -278,19 +265,13 @@ extern char * target_fp_name;
case instruction scheduling becomes very uninteresting. */ case instruction scheduling becomes very uninteresting. */
#define ARM_FLAG_FPE (0x0004) #define ARM_FLAG_FPE (0x0004)
/* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
of condition flags when returning from a branch & link (ie. a function) */
/* ********* DEPRECATED ******** */
#define ARM_FLAG_ARM6 (0x0008)
/* ********* DEPRECATED ******** */
#define ARM_FLAG_ARM3 (0x0010)
/* Nonzero if destined for a processor in 32-bit program mode. Takes out bit /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
that assume restoration of the condition flags when returning from a that assume restoration of the condition flags when returning from a
branch and link (ie a function). */ branch and link (ie a function). */
#define ARM_FLAG_APCS_32 (0x0020) #define ARM_FLAG_APCS_32 (0x0020)
/* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
/* Nonzero if stack checking should be performed on entry to each function /* Nonzero if stack checking should be performed on entry to each function
which allocates temporary variables on the stack. */ which allocates temporary variables on the stack. */
#define ARM_FLAG_APCS_STACK (0x0040) #define ARM_FLAG_APCS_STACK (0x0040)
...@@ -331,8 +312,6 @@ function tries to return. */ ...@@ -331,8 +312,6 @@ function tries to return. */
#define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME) #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
#define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
#define TARGET_FPE (target_flags & ARM_FLAG_FPE) #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
#define TARGET_6 (target_flags & ARM_FLAG_ARM6)
#define TARGET_3 (target_flags & ARM_FLAG_ARM3)
#define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
#define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
...@@ -368,9 +347,6 @@ function tries to return. */ ...@@ -368,9 +347,6 @@ function tries to return. */
{"poke-function-name", ARM_FLAG_POKE, \ {"poke-function-name", ARM_FLAG_POKE, \
"Store function names in object code" }, \ "Store function names in object code" }, \
{"fpe", ARM_FLAG_FPE, "" }, \ {"fpe", ARM_FLAG_FPE, "" }, \
{"6", ARM_FLAG_ARM6, "" }, \
{"2", ARM_FLAG_ARM3, "" }, \
{"3", ARM_FLAG_ARM3, "" }, \
{"apcs-32", ARM_FLAG_APCS_32, \ {"apcs-32", ARM_FLAG_APCS_32, \
"Use the 32bit version of the APCS" }, \ "Use the 32bit version of the APCS" }, \
{"apcs-26", -ARM_FLAG_APCS_32, \ {"apcs-26", -ARM_FLAG_APCS_32, \
......
gcc/config/arm/arm.md
...@@ -1194,24 +1194,24 @@ ...@@ -1194,24 +1194,24 @@
" "
[(set_attr "conds" "set")]) [(set_attr "conds" "set")])
(define_insn "*zeroextractqi_compare0_scratch" (define_insn "*ne_zeroextractsi"
[(set (reg:CC_NOOV 24) [(set (match_operand:SI 0 "s_register_operand" "=r")
(compare:CC_NOOV (zero_extract:SI (ne:SI (zero_extract:SI
(match_operand:QI 0 "memory_operand" "m") (match_operand:SI 1 "s_register_operand" "r")
(match_operand 1 "const_int_operand" "n") (match_operand:SI 2 "const_int_operand" "n")
(match_operand 2 "const_int_operand" "n")) (match_operand:SI 3 "const_int_operand" "n"))
(const_int 0))) (const_int 0)))]
(clobber (match_scratch:QI 3 "=r"))] "INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32
"INTVAL (operands[2]) >= 0 && INTVAL (operands[1]) > 0 && INTVAL (operands[2]) > 0
&& ((INTVAL (operands[2]) + INTVAL (operands[1])) <= 8)" && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8
&& INTVAL (operands[2]) + INTVAL (operands[3]) <= 32"
"* "*
operands[1] = GEN_INT (((1 << INTVAL (operands[1])) - 1) operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1)
<< INTVAL (operands[2])); << INTVAL (operands[3]));
output_asm_insn (\"ldr%?b\\t%3, %0\", operands); output_asm_insn (\"ands\\t%0, %1, %2\", operands);
output_asm_insn (\"tst%?\\t%3, %1\", operands); return \"movne\\t%0, #1\";
return \"\";
" "
[(set_attr "conds" "set") [(set_attr "conds" "clob")
(set_attr "length" "8")]) (set_attr "length" "8")])
;;; ??? This pattern is bogus. If operand3 has bits outside the range ;;; ??? This pattern is bogus. If operand3 has bits outside the range
...@@ -2711,11 +2711,15 @@ ...@@ -2711,11 +2711,15 @@
" [(set_attr "type" "load")]) " [(set_attr "type" "load")])
(define_insn "pic_add_dot_plus_eight" (define_insn "pic_add_dot_plus_eight"
[(set (pc) (label_ref (match_operand 0 "" ""))) [(set (match_operand 0 "register_operand" "+r")
(set (match_operand 1 "register_operand" "+r") (plus:SI (match_dup 0) (const (plus:SI (pc) (const_int 8)))))
(plus:SI (match_dup 1) (const (plus:SI (pc) (const_int 8)))))] (use (label_ref (match_operand 1 "" "")))]
"flag_pic" "flag_pic"
"add%?\\t%1, %|pc, %1") "*
ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
CODE_LABEL_NUMBER (operands[1]));
return \"add%?\\t%0, %|pc, %0\";
")
;; If copying one reg to another we can set the condition codes according to ;; If copying one reg to another we can set the condition codes according to
;; its value. Such a move is common after a return from subroutine and the ;; its value. Such a move is common after a return from subroutine and the
......
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