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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
df5f5124
Commit
df5f5124
authored
Oct 05, 1993
by
Jim Wilson
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(sched_analyze_2): Make volatile asms depend on all
pseudo registers. From-SVN: r5621
parent
67c8d7de
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gcc/sched.c
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gcc/sched.c
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df5f5124
...
...
@@ -1940,11 +1940,16 @@ sched_analyze_2 (x, insn)
rtx
u
;
/* Traditional and volatile asm instructions must be considered to use
and clobber all hard registers and all of memory. So must
TRAP_IF and UNSPEC_VOLATILE operations. */
and clobber all hard registers, all pseudo-registers and all of
memory. So must TRAP_IF and UNSPEC_VOLATILE operations.
Consider for instance a volatile asm that changes the fpu rounding
mode. An insn should not be moved across this even if it only uses
pseudo-regs because it might give an incorrectly rounded result. */
if
(
code
!=
ASM_OPERANDS
||
MEM_VOLATILE_P
(
x
))
{
for
(
i
=
0
;
i
<
FIRST_PSEUDO_REGISTER
;
i
++
)
int
max_reg
=
max_reg_num
();
for
(
i
=
0
;
i
<
max_reg
;
i
++
)
{
for
(
u
=
reg_last_uses
[
i
];
u
;
u
=
XEXP
(
u
,
1
))
add_dependence
(
insn
,
XEXP
(
u
,
0
),
REG_DEP_ANTI
);
...
...
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