Skip to content

R
riscv-gcc-1
Commit dec21bbc by Kyrylo Tkachov Committed by Kyrylo Tkachov
Options

[ARM][3/4] Cleanup casts from INTVAL to [unsigned] HOST_WIDE_INT 

	* config/arm/arm.md (ashldi3): Replace comparison of INTVAL of
	operands[2] against 1 with comparison against CONST1_RTX.
	(ashrdi3): Likewise.
	(lshrdi3): Likewise.
	(ashlsi3): Replace cast of INTVAL to unsigned HOST_WIDE_INT with
	UINTVAL.
	(ashrsi3): Likewise.
	(lshrsi3): Likewise.
	(rotrsi3): Likewise.
	(define_split above *compareqi_eq0): Likewise.
	(define_split above "prologue"): Likewise.
	* config/arm/arm.c (thumb1_size_rtx_costs): Likewise.
	* config/arm/predicates.md (shift_operator): Likewise.
	(shift_nomul_operator): Likewise.
	(sat_shift_operator): Likewise.
	(thumb1_cmp_operand): Likewise.
	(const_neon_scalar_shift_amount_operand): Replace manual range
	check with IN_RANGE.
	* config/arm/thumb1.md (define_peephole2 above *thumb_subdi3):
	Replace cast of INTVAL to unsigned HOST_WIDE_INT with UINTVAL.

From-SVN: r236640
parent a04e69c0
Showing with 43 additions and 24 deletions
gcc/ChangeLog
2016-05-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.md (ashldi3): Replace comparison of INTVAL of
operands[2] against 1 with comparison against CONST1_RTX.
(ashrdi3): Likewise.
(lshrdi3): Likewise.
(ashlsi3): Replace cast of INTVAL to unsigned HOST_WIDE_INT with
UINTVAL.
(ashrsi3): Likewise.
(lshrsi3): Likewise.
(rotrsi3): Likewise.
(define_split above *compareqi_eq0): Likewise.
(define_split above "prologue"): Likewise.
* config/arm/arm.c (thumb1_size_rtx_costs): Likewise.
* config/arm/predicates.md (shift_operator): Likewise.
(shift_nomul_operator): Likewise.
(sat_shift_operator): Likewise.
(thumb1_cmp_operand): Likewise.
(const_neon_scalar_shift_amount_operand): Replace manual range
check with IN_RANGE.
* config/arm/thumb1.md (define_peephole2 above *thumb_subdi3):
Replace cast of INTVAL to unsigned HOST_WIDE_INT with UINTVAL.
2016-05-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.md (andsi3): Replace cast of 1 to HOST_WIDE_INT
with HOST_WIDE_INT_1.
(insv): Likewise.
......
gcc/config/arm/arm.c
......@@ -9061,7 +9061,7 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
case CONST_INT:
if (outer == SET)
{
if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
if (UINTVAL (x) < 256)
return COSTS_N_INSNS (1);
/* See split "TARGET_THUMB1 && satisfies_constraint_J". */
if (INTVAL (x) >= -255 && INTVAL (x) <= -1)
......
gcc/config/arm/arm.md
......@@ -3747,8 +3747,7 @@
{
rtx scratch1, scratch2;
if (CONST_INT_P (operands[2])
&& (HOST_WIDE_INT) INTVAL (operands[2]) == 1)
if (operands[2] == CONST1_RTX (SImode))
{
emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1]));
DONE;
......@@ -3793,7 +3792,7 @@
"TARGET_EITHER"
"
if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
&& (UINTVAL (operands[2])) > 31)
{
emit_insn (gen_movsi (operands[0], const0_rtx));
DONE;
......@@ -3821,8 +3820,7 @@
{
rtx scratch1, scratch2;
if (CONST_INT_P (operands[2])
&& (HOST_WIDE_INT) INTVAL (operands[2]) == 1)
if (operands[2] == CONST1_RTX (SImode))
{
emit_insn (gen_arm_ashrdi3_1bit (operands[0], operands[1]));
DONE;
......@@ -3867,7 +3865,7 @@
"TARGET_EITHER"
"
if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
&& UINTVAL (operands[2]) > 31)
operands[2] = GEN_INT (31);
"
)
......@@ -3892,8 +3890,7 @@
{
rtx scratch1, scratch2;
if (CONST_INT_P (operands[2])
&& (HOST_WIDE_INT) INTVAL (operands[2]) == 1)
if (operands[2] == CONST1_RTX (SImode))
{
emit_insn (gen_arm_lshrdi3_1bit (operands[0], operands[1]));
DONE;
......@@ -3938,7 +3935,7 @@
"TARGET_EITHER"
"
if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
&& (UINTVAL (operands[2])) > 31)
{
emit_insn (gen_movsi (operands[0], const0_rtx));
DONE;
......@@ -3972,7 +3969,7 @@
if (TARGET_32BIT)
{
if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
&& UINTVAL (operands[2]) > 31)
operands[2] = GEN_INT (INTVAL (operands[2]) % 32);
}
else /* TARGET_THUMB1 */
......@@ -5120,7 +5117,7 @@
(match_operator 5 "subreg_lowpart_operator"
[(match_operand:SI 4 "s_register_operand" "")]))))]
"TARGET_32BIT
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[3])
&& (UINTVAL (operands[3])
== (GET_MODE_MASK (GET_MODE (operands[5]))
& (GET_MODE_MASK (GET_MODE (operands[5]))
<< (INTVAL (operands[2])))))"
......@@ -10224,8 +10221,8 @@
(match_operand 1 "const_int_operand" "")))
(clobber (match_scratch:SI 2 ""))]
"TARGET_ARM
&& (((unsigned HOST_WIDE_INT) INTVAL (operands[1]))
== (((unsigned HOST_WIDE_INT) INTVAL (operands[1])) >> 24) << 24)"
&& ((UINTVAL (operands[1]))
== ((UINTVAL (operands[1])) >> 24) << 24)"
[(set (match_dup 2) (zero_extend:SI (match_dup 0)))
(set (reg:CC CC_REGNUM) (compare:CC (match_dup 2) (match_dup 1)))]
"
......
gcc/config/arm/predicates.md
......@@ -170,8 +170,7 @@
(define_predicate "const_neon_scalar_shift_amount_operand"
(and (match_code "const_int")
(match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode)
&& ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0")))
(match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))")))
(define_predicate "ldrd_strd_offset_operand"
(and (match_operand 0 "const_int_operand")
......@@ -285,19 +284,19 @@
(match_test "power_of_two_operand (XEXP (op, 1), mode)"))
(and (match_code "rotate")
(match_test "CONST_INT_P (XEXP (op, 1))
&& ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
&& (UINTVAL (XEXP (op, 1))) < 32")))
(and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
(match_test "!CONST_INT_P (XEXP (op, 1))
|| ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
|| (UINTVAL (XEXP (op, 1))) < 32")))
(match_test "mode == GET_MODE (op)")))
(define_special_predicate "shift_nomul_operator"
(and (ior (and (match_code "rotate")
(match_test "CONST_INT_P (XEXP (op, 1))
&& ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))
&& (UINTVAL (XEXP (op, 1))) < 32"))
(and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
(match_test "!CONST_INT_P (XEXP (op, 1))
|| ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
|| (UINTVAL (XEXP (op, 1))) < 32")))
(match_test "mode == GET_MODE (op)")))
;; True for shift operators which can be used with saturation instructions.
......@@ -306,7 +305,7 @@
(match_test "power_of_two_operand (XEXP (op, 1), mode)"))
(and (match_code "ashift,ashiftrt")
(match_test "CONST_INT_P (XEXP (op, 1))
&& ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)")))
&& (UINTVAL (XEXP (op, 1)) < 32)")))
(match_test "mode == GET_MODE (op)")))
;; True for MULT, to identify which variant of shift_operator is in use.
......@@ -532,7 +531,7 @@
(ior (and (match_code "reg,subreg")
(match_operand 0 "s_register_operand"))
(and (match_code "const_int")
(match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
(match_test "(UINTVAL (op)) < 256"))))
(define_predicate "thumb1_cmpneg_operand"
(and (match_code "const_int")
......
gcc/config/arm/thumb1.md
......@@ -114,8 +114,8 @@
(set (match_dup 0)
(plus:SI (match_dup 0) (reg:SI SP_REGNUM)))]
"TARGET_THUMB1
&& (unsigned HOST_WIDE_INT) (INTVAL (operands[1])) < 1024
&& (INTVAL (operands[1]) & 3) == 0"
&& UINTVAL (operands[1]) < 1024
&& (UINTVAL (operands[1]) & 3) == 0"
[(set (match_dup 0) (plus:SI (reg:SI SP_REGNUM) (match_dup 1)))]
""
)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment